Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Physical design processing
Reexamination Certificate
2011-08-16
2011-08-16
Garbowski, Leigh Marie (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Integrated circuit design processing
Physical design processing
C716S109000, C716S136000
Reexamination Certificate
active
08001508
ABSTRACT:
A method for optimizing pin selection for an integrated circuit is provided. Pin locations are mapped to a vector. The mutual inductive relationships between pins of the integrated circuit are captured into a matrix. The matrix contains the data of how a signal state of each pin is affected by the toggling of other pins within the I/O bank. The pin locations and the crosstalk matrix are combined to characterize the impact of the crosstalk on the pins for the pin placement. Thereafter, a user may decide to alter the pin placement or alter the sampling interval for the pin to avoid sampling the pin when the crosstalk may affect the signal integrity. The method may be applied for multiple simultaneous switching noise cause mechanisms impacting the signal integrity. In this embodiment, a worst case cause mechanism from the individually quantified cause mechanisms is determined by comparing an impact of each of the cause mechanisms.
REFERENCES:
patent: 6102960 (2000-08-01), Berman et al.
patent: 6868374 (2005-03-01), Ditlow et al.
patent: 7454301 (2008-11-01), Daud et al.
Chun et al., “Model to Hardware Correlation for Power Distribution Induced I/O Noise in a Functioning Comptuer System,” 2002 Electronic Components and Technology Conference, pp. 319-324.
Liu et al., “Analyzing FPGA Simultaneous Switching Noise in Printed CIrcuit Boards,” 2006 IEEE, pp. 377-382.
Shi et al., “Simultaneous Switching Noise in FPGA and Structure ASIC Devices, Methodologies for ANalysis, Modeling, and Validation,” 2006 Electronic Components and Technology Conference, pp. 229-236.
Secker et al., “Effects and Modeling of Simultaneous Switching Noise for BiCMOS Off-Chip Drivers,” IEEE Trans. on Components, Packaging, and Manufacturing Technology—Part B, vol. 19, No. 3, Aug. 1996, pp. 473-480.
Suresh et al., “Package-silicon co-design—Experiment with an SOC deisgn,” Proc. of the 17thInt'l Conference on VLSI Design (VLSI'04), 2004 IEEE, 6 pages.
Daud Nafira
Liu Geping
Smith Lawrence David
Wong San
Altera Corporation
Garbowski Leigh Marie
Martine & Penilla & Gencarella LLP
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