Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-08-08
2006-08-08
Elmore, Stephen C. (Department: 2185)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S118000, C711S144000, C711S154000, C711S156000, C711S159000, C715S748000
Reexamination Certificate
active
07089365
ABSTRACT:
Disclosed is a central cache that is updated without the overhead of locking. Updates are “atomic” in that they cannot be interrupted part way through. Applications are always free to read data in the cache, accessing the data through a reference table. Applications do not directly update the cache, instead, they send update requests to a service routine. To update the cache, the service routine proceeds in two phases. In the first phase, the service routine prepares the new data and adds them to the cache, without updating the reference table. During the first phase, an application accessing the cache cannot “see” the new data because the reference table has not yet been updated. After the first phase is complete, the service routine performs the second phase of the update process: atomically updating the reference table. The two-phase update process leaves the cache, at all times, in a consistent state.
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Brown David C.
Byrd Michael M.
Leonov Mikhail V.
Elmore Stephen C.
Merchant & Gould LLC
Microsoft Corporation
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