Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1996-07-29
2001-10-02
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06298469
ABSTRACT:
FIELD OF THE INVENTION
The present invention is directed toward generating integrated circuits and more particularly to a system and method for producing an integrated circuit that can be portably produced regardless of the manufacturing process.
BACKGROUND OF THE INVENTION
Integrated circuits are designed in a variety of fashions for a variety of purposes. Initially, a custom cell or megacell is designed which comprises a collection of gates and transistors and interconnections therebetween.
For a conventional circuit, there is a preexisting integrated circuit design environment including a schematic capture station, a logic simulator, timing verifier, and circuit simulator. The hardware of such design environments generally minimally comprises a computer, keyboard, graphic display means (such as a color graphic CRT display system), and graphic input means (such as a mouse or a digitizing tablet). Generally the hardware would be based upon a commercially available computer workstation, such as those provided by Sun Microsystems or by Apollo Computer Incorporated, and the software of the design environment would be provided as an set of tools by one or more cadence manufacturer, such as the design environments provided by Mentor Graphics Incorporated. There also exists a logic schematic prepared on the schematic capture station for which an accurate logic simulation is desired, and from which a net-list has been prepared. A net-list is a file comprising descriptions of the logic primitives (e.g., AND/OR gates, etc.) used in the logic schematic and the connectivity therebetween. This is generally accomplished automatically by the schematic capture system upon completion of the logic schematic, although some systems may require an additional step of logic compilation, whereby the user invokes a program to perform the process of conversion of the graphical schematic data to a net-list. In any case, the capability of net-list generation is widely known and implemented in all present schematic design environments.
Traditionally, the physical layout design is done with physical layout tools, known generically as “polygon editor”. Experienced layout designers are employed to manually design such integrated circuits with the sole objective of creating a very area efficient design. One of the most important constraints in a layout design is the process layout design rules, which specify the spatial characteristics and limits of each process mask layer and the relationships between multiple layers. These design rules are process technology specific. The major drawbacks of the traditional approach in custom cell (integrated circuit) design are (1) time consuming, (2) not easily adaptable to new processes, and (3) very poor in terms of logic/timing simulation capability.
In addition, it is not possible to provide an accurate simulation model for such integrated circuits. Typically, “behavioral model” is used to describe the functionality of the cell. “Behavioral models” in great majority of cases do not adequately model the cells′ functional and timing characteristics. Furthermore, there is often a need to have the same custom cells in different “processes”(as in fabrication), either to increase circuit performance, or to have alternate sources for the product or to be integrated in another design. Accordingly, what is needed is a system which allows for the migration of a particular integrated circuit portably from one process to another process quickly and accurately. In addition, what is needed is a design methodology that will allow for an integrated circuit design to be used over and over again with only minor modifications and within a variety of process environments. The present invention addresses such a need.
SUMMARY OF THE INVENTION
A method and system for taking a first integrated circuit from a first manufacturing process and generating a second integrated circuit for a second manufacturing process is disclosed. The method and system comprises providing a first library from the first integrated circuit, the first library defining the characteristics of the first gate array, and mapping and characterizing the first library from the first integrated circuit into a set of design criteria for the second manufacturing process.
The method and system in accordance with the second aspect also includes generating a plurality of a methodology and system of databases representing libraries and information about the design. The database will include the following information: physical cell library, logic device library, timing model library for the logic devices, design netlist and physical connectivity of the logic devices. In addition, the integrated circuit's physical size, functional behavior and timing characteristics are fully defined by the above database. The method and system in accordance with the present invention also enables mapping of physical database to allow for the recharacterizing of the timing models from one IC fabrication process to any other IC fabrication process. Accordingly through a system and method in accordance with the present invention, an integrated circuit can be portably manufactured on a plurality of different manufacturing processes. The method and system therefore has significant advantages over known conventional integrated circuit design processes.
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Lisanke, Robert et al., “McMAP: A Fast Technology Mapping Procedure for Multi-Level Logic Synthesis,”IEEE, New York, NY, Oct. 3-5, 1988, pp. 252-256.
Aspec Technology, Inc.
Sawyer Law Group LLP
Siek Vuthe
Smith Matthew
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