Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2008-03-24
2010-11-16
Chiang, Jack (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C703S019000
Reexamination Certificate
active
07836418
ABSTRACT:
The invention generally relates to integrated circuit design, and more particularly to systems and methods for providing power optimization in a hierarchical netlist. A method includes generating a hierarchical netlist of the design, wherein the design includes a plurality of macros. The method also includes determining the timing slack of each path of the design. For each pin of each one of the plurality of macros, the method includes: determining the worst timing path; determining the slack value of the worst timing path; determining the subset of macros of the plurality of macros associated with the worst timing path; determining an apportionment parameter for each one of the subset of macros; determining a distribution of the slack amongst the subset of macros based upon the respective apportionment parameters; and adjusting timing assertions for each one of the subset of macros based upon the distribution of the slack.
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patent: 7003747 (2006-02-01), Zhou et al.
patent: 7093208 (2006-08-01), Williams et al.
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Binder William A.
Gonzalez Christopher J.
Kartschoke Paul D.
Murphy, Jr. Sherwin C.
Chiang Jack
International Business Machines - Corporation
Kotulak Richard
Nguyen Nha T
Roberts Mlotkowski Safran & Cole
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