Electrical computers and digital processing systems: memory – Address formation – Address mapping
Reexamination Certificate
1999-03-29
2001-08-07
Verbrugge, Kevin (Department: 2185)
Electrical computers and digital processing systems: memory
Address formation
Address mapping
Reexamination Certificate
active
06272613
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a process for accessing a storage area in the physical addressing mode, the storage area of a digital data processing machine also being accessible in a virtual addressing mode. The present invention also relates to a digital data processing machine comprising a storage area that is accessible in both the physical addressing mode and the virtual addressing mode.
2. Description of Related Art
The virtual addressing mode makes it possible to allocate one or more segments of virtual memory in a virtual address space to a process currently being executed in the machine. A segment of virtual memory is traditionally constituted by pages of fixed size, each accessible by means of a logical page number. When a storage area of the machine is accessible by means of virtual addresses, each constituted by a logical page number and a relative address, during access a given physical page number corresponds to the logical page number in question. The relative address is what indicates the address within a logical page. The size of the physical page is identical to that of the virtual page. Real access to the storage area of the machine is gained by means of a known mechanism that translates the virtual address into a physical address constituted by the physical page number and the relative address. The advantage of a virtual address space is that it represents an addressing potentiality that is available for a process or a thread of this process without the need to be concerned with the actual existence of a physical page in memory or with the location of this page in physical memory if it exists. Since the correspondence between the logical page number and the physical page number is generated by an effective access of the process to the virtual address, two contiguous logical page numbers do not necessarily correspond to two contiguous physical page numbers in physical memory.
The physical addressing mode enables a process or a thread of this process to access the physical memory directly without using the known mechanism for translating a virtual address into a physical address as mentioned above. This addressing mode is particularly useful for certain functions of the operating system of the machine. For example, the above-mentioned mechanism can use the physical addressing mode.
A storage area necessary to the execution of a process can cover more than one physical page of the machine. The storage area can be used, for example, to contain executable instruction code or data like that contained in a stack, a buffer, or an array. To access the storage area, the process performs address calculations required by the reading of an instruction line that follows a current instruction, or of an instruction line defined by a jump in the case where the storage area contains executable instruction code; the process also performs address calculations required by the reading or writing of a datum that follows a previously processed datum, or of a datum located at a fixed distance from a previously processed datum.
In the virtual addressing mode, these calculations are performed on logical addresses. The storage area is accessed by means of logical page numbers forming a continuous sequence. Likewise, the calculation of a new address that follows a current address is performed simply by adding a whole number to the current address. The case in which the new address is constituted by a logical page number different from that of the current address does not pose any particular problem. It matters little that the physical pages accessed in the storage area constitute a fragmented set. The mechanism for managing the virtual address space takes care of creating an appropriate correspondence between the logical page number and the physical page number.
However, a problem arises when using the physical addressing mode to access the storage area if the physical page numbers that cover it do not constitute a continuous sequence. In effect, a simple addition to a current address runs the risk of generating a physical page number that is not allocated to the storage area. Moreover, the mechanism for managing the virtual address space generally allows the physical page numbers allocated to the storage area to change during the execution of different processes in the machine.
One usual solution is to reserve a storage area accessible in the physical addressing mode as soon as the machine starts up, by reserving a continuous sequence of physical page numbers that are locked, i.e., whose allocation cannot be modified by the virtual addressing mechanism while the machine is in operation.
The usual solution has many drawbacks. The reserved physical page numbers reduce the possibilities for the virtual memory managing mechanism to map physical page numbers to logical page numbers. Difficulties arise when defining in the virtual addressing mode a storage area accessible in the physical addressing mode, at any instant in the operation of the machine, since there is a high risk that the mechanism for managing the virtual address space will map the logical page numbers to physical page numbers that do not constitute a continuous sequence.
SUMMARY OF THE INVENTION
To mitigate the above-mentioned drawbacks, the invention proposes a process for accessing a storage area of a digital data processing machine in the physical addressing mode, said storage area also being accessible in the virtual addressing mode by means of virtual addresses, each constituted by a logical page number and a relative address, a first logical page number in question corresponding to a first given physical page number, and a second logical page number contiguous to the first logical page number in question corresponding to a second physical page number not necessarily contiguous to said given physical page number, characterized in that it is comprised of writing, at the address constituted by the first logical page number in question and by a relative address having a first predetermined value, said second physical page number.
Thus, it is possible to access the same storage area of a digital data processing machine in both the physical addressing mode and the virtual addressing mode.
According to a particular mode of implementation, the process is characterized in that each incrementation of an old current address, a new relative address is produced in response to each incrementation of the old current address and triggers a comparison of the new relative address to the first predetermined relative address value and generates a new current address such that:
the new current address is constituted by the first logical page number in question for the virtual addressing mode, by the corresponding physical page number for the physical addressing mode, and by the new relative address produced if the new relative address is less than the relative address having the first predetermined value,
the new current address is constituted by a second logical page number contiguous to the logical page number in question for the virtual addressing mode, by the second physical page number for the physical addressing mode, and by a relative address having a second predetermined value if the new relative address is greater than or equal to the relative address having the first predetermined value.
REFERENCES:
patent: 4279014 (1981-07-01), Cassonnet
patent: 4951194 (1990-08-01), Bradley et al.
patent: 5220669 (1993-06-01), Baum et al.
patent: 5274811 (1993-12-01), Borg et al.
patent: 0566421 (1993-10-01), None
Bouraoui Nadia
Mazzilli Jean-Pascal
Sorace Jean-Dominique
Bull S.A.
Kondracki Edward J.
Miles & Stockbridge P.C.
Verbrugge Kevin
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