Method and system for accelerating ethernet checksums

Details Method and system for accelerating ethernet checksums Method and system for accelerating ethernet checksums

2005-08-30

2005-08-30

Torres, Joseph D. (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S779000

Reexamination Certificate

active

06938198

ABSTRACT:
A method for computing Ethernet checksums for implementing ECC processing within high performance digital transmission networks. The method includes the step of receiving an input data word and receiving an input CRC. The input data word can be 64 bits. The input CRC can be 32 bits. The input data word and the input CRC are combined using an exclusive-or function to obtain a data-CRC combination. The data-CRC combination is then positioned with respect to a time line reference. The data-CRC combination is positioned by extending the data-CRC combination with a number of future bits and shifting the extended data-CRC combination with respect to the time line reference. An output CRC is then computed for the extended data-CRC combination. The output CRC can be computed without regard to a number of valid data bits of the input data word.

REFERENCES:
patent: 3678469 (1972-07-01), Freeman et al.
patent: 6804257 (2004-10-01), Benayoun et al.
TDB-ACC-NO: NN72091314,“Parallel CRC Generation for Multilength Characters”, Sep. 1972, IBM Technical Disclosure Bulletin, Sep. 1972.
TDB-ACC-NO: NN930251,“Cyclic Redundancy Code Computation for a Variable Length Data”, Feb. 1993, IBM Technical Disclosure Bulletin.

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