Method and system for a RFIC master

Details Method and system for a RFIC master Method and system for a RFIC master

2006-02-14

2009-08-18

Rinehart, Mark (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C710S306000, C710S315000, C712S037000, C712S038000, C455S418000, C455S419000, C455S466000

Reexamination Certificate

active

07577779

ABSTRACT:
Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.

REFERENCES:
patent: 5790817 (1998-08-01), Asghar et al.
patent: 5920891 (1999-07-01), Steinbach et al.
patent: 6029239 (2000-02-01), Brown
patent: 6785556 (2004-08-01), Souissi
patent: 6952594 (2005-10-01), Hendin
patent: 7197578 (2007-03-01), Jacobs
patent: 7296186 (2007-11-01), So et al.
patent: 2002/0159434 (2002-10-01), Gosior et al.
patent: 2003/0067902 (2003-04-01), Skeba
patent: 2003/0203720 (2003-10-01), Oosawa et al.
patent: 2004/0185899 (2004-09-01), Hayem et al.
patent: 2004/0204038 (2004-10-01), Suzuki et al.
patent: 2004/0225783 (2004-11-01), Erickson et al.
patent: 2005/0064856 (2005-03-01), Atkin et al.
patent: 2005/0064892 (2005-03-01), Cavin
patent: 2005/0094584 (2005-05-01), Kluge et al.
patent: 2005/0107077 (2005-05-01), Hintermeier et al.
patent: 2006/0004938 (2006-01-01), Matthews et al.
patent: 2006/0031618 (2006-02-01), Hansquine et al.
patent: 2007/0090874 (2007-04-01), Sorrells et al.
patent: 2007/0161459 (2007-07-01), Watson
patent: 2009/0104900 (2009-04-01), Lee
patent: 06120949 (1994-04-01), None
patent: 2003332441 (2003-11-01), None
patent: 2007208427 (2007-08-01), None
Shimpi, Anand Lal, “Intel Pentium 4 2.0 GHz: The clock strikes two”, Aug. 27, 2001, AnandTech, p. 2, retrieved from the Internet on Dec. 19, 2008 at http://www.anandtech.com/printarticle.aspx?i=1524.
“PCI Local Bus Specification”, Revision 2.1, Jun. 1, 1995, PCI Special Interest Group, p. 4.
Definition of “CPU”, Microsoft Computer Dictionary, Fifth Edition, 2002, Microsoft Corporation, p. 132.
Mullen, Robert A., “RF Design Methodologies Bridging System-IC-Module Design”, Jan. 2004, IEEE Press, Proceedings of the 2004 conference on Asia South Pacific design automation: electronic design and solution fair with EDA Technofair Design Automation Conference Asia and South Pacific, pp. 491-498.
Kim, Bruce C.; Force, Craig, “Guest Editors' Introduction: The Evolution of RFIC Design and Test,” Design & Test of Computers, IEEE, vol. 25, No. 1, pp. 6-8, Jan.-Feb. 2008.
Ferrario, J.; Wolf, R.; Moss, S.; Slamani, M., “A low-cost test solution for wireless phone RFICs,” Communications Magazine, IEEE, vol. 41, No. 9, pp. 82-88, Sep. 2003.

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