Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-04-13
2003-10-21
McLean-Mayo, Kimberly (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S145000
Reexamination Certificate
active
06636948
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to modular multiprocessor computing systems and, in particular to coherent cache control in such systems, and even more particularly to controlling the gaining of ownership of cached data, by a processor that wants to write or up-date the data, in a manner that enhances the system's performance.
2. Background Information
Modular multiprocessor computing systems typically have a number of multi-processor nodes interconnected via switching fabric. Each node includes multiple processors, memory arrays, and input/output access hardware, and the interconnecting switching mechanisms. Cache memory, also referred to as “cache,” is routinely found in these system.
These modular multiprocessor systems share many resources including memory. However, in such large systems, cache is usually associated with a particular processor and holds the data that that processor is likely to access in the near future. However, input/output ports may also have such private caches. In these large systems the processor and/or the input/output ports may update the contents of their private caches without updating shared memory, and a cache coherent protocol is often utilized to maintain data consistency and accuracy of the data. In such systems the control of the cache becomes complex and operations thereon can significantly affect the efficiency and/or speed of the entire processing system.
If a remote processor has a copy of data, say by earlier executing a read-miss, and that remote processor wants to write the data, that remote processor must gain ownership of the data. Ownership could be gained by executing a write-miss, but in this case the system must return a copy of the data itself. It would be more efficient to have ownership of the data returned by performing a change-to-dirty (CTD) operation. However, the CTD operation must succeed or the system performance could be seriously degraded.
In these large systems memory operations usually include both reads and writes. Such systems are implemented to support both read and write miss operations. If data or a datum is to be both read and then written, system designers have added a change-to-dirty (CTD or XTD) operation that is used when a processor has a copy of the data and want to write the data.
In some systems the organization of the cache is in blocks, lines or clusters of lines. The data stored in a cache is exclusive to one owner, where that owner has direct control of the data. In operation a data segment ownership may be claimed by a processor with an up-to-date copy of the data by executing the change-to-dirty operation which may grant ownership of the data cache block to the processor. Here a “dirty” state of data denotes the unique most up-to-date copy of the data in the system. If the CTD is successful and the processor gains ownership, invalidations (Invals) are sent to all other processors (usually listed in a directory) having copies in the system. These Invals inform the remote processor that they have out of date copies of the data. The owner of the data may then change the contents of the data.
If the CTD is unsuccessful, the copy of the data held by the processor is not up-to-date, a newer version has been created and an Inval is headed to this processor. In this case there may be several processors trying to obtain ownership of the data and many failures and Invals may be being transmitted across the system. This occurrence presents a performance issue for multiprocessor systems that is being addressed by this invention.
Another performance issue that the above CTD operations presents is that the directory, where the addresses of processors having versions of the data is kept, must be complete and large enough to accurately answer success or failure of the CTD operations, or some other higher-level entity must be implemented to ensure accurate answers to the success or failures of CTD operations.
The present invention is directed to ensuring that CTD operations succeed, thereby eliminating the above limitations of unsuccessful CTD operations and the need for an expanded or adjunct directory system.
SUMMARY OF THE INVENTION
The limitations of the prior art and objects and advantages of the present invention are addressed a method and system that ensures that a processor in a multiprocessor system with a copy of data gains assured ownership and an up-to-date copy of data so that the processor can write or change the data.
The processor, having a copy of the data but not ownership, issues a change-to-dirty command, CTD, requesting ownership of the data. Preferably the request is directed to a directory where the location and ownershiip of the up-to-date data is maintained. The directory returns a success response, CTD-success, to the processor if the first processor is unambiguously determined to have an up-to-date copy of the data. The ownership of the data is updated in the directory.
If the processor does not unambiguously have an up-to-date copy of the data, a wait for success, CTD-check-Ok, is sent to the processor. A command is then sent to the owner of the up-to-date copy of the data to send the data to the requesting processor and then updating the ownership of the data in the directory.
REFERENCES:
patent: 6094686 (2000-07-01), Sharma
patent: 6405292 (2002-06-01), Joseph et al.
patent: 6477620 (2002-11-01), Bauman et al.
patent: 6493801 (2002-12-01), Steely, Jr. et al.
Sharna Madhu
Steely, Jr. Simon C.
Van Doren Stephen R.
Hewlett-Packard Development Company LP.
McLean-Mayo Kimberly
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