Method and system for a multi-level virtual/real cache...

Details Method and system for a multi-level virtual/real cache... Method and system for a multi-level virtual/real cache...

2008-02-25

2011-10-18

Patel, Hetul (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711S210000, C711SE12024

Reexamination Certificate

active

08041894

ABSTRACT:
Method and system for a multi-level virtual/real cache system with synonym resolution. An exemplary embodiment includes a multi-level cache hierarchy, including a set of L1 caches associated with one or more processor cores and a set of L2 caches, wherein the set of L1 caches are a subset of the set of L2 caches, wherein the set of L1 caches underneath a given L2 cache are associated with one or more of the processor cores.

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patent: 6751720 (2004-06-01), Barroso et al.
Hunt, et al. “Early Resolution of Address Translation in Cache Design”. Proceedings—IEEE International Conference on Computer Design: VLSI in Computers and Processors, Sep. 1990, pp. 408-412.
Wang, et al. “Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy”. Conference Proceedings—Annual Symposium on Computer Architecture, No. 16, May 1989. pp. 140-148.
Kim, et al. “A solution to the synonym problem of virtual caches based on implicit flushing”. Journal of KISS (A). Computer Systems and Theory. vol. 24. No. 11. Nov. 1997. pp. 1207(English Abstract included).
z/Architecture. “Principles of Operation”. Sixth Edition (Apr. 2007). IBM. 1218 pages.

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