Method and system for a multi-channel add-compare-select unit

Details Method and system for a multi-channel add-compare-select unit Method and system for a multi-channel add-compare-select unit

2003-11-18

2009-11-03

Tu, Christine T (Department: 2117)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S798000, C714S745000

Reexamination Certificate

active

07613990

ABSTRACT:
A circuit for a multi-channel add-compare-select unit is disclosed. The circuit includes a compare unit and a datapath. The datapath is coupled to the compare unit, and includes a number of adder units, a selection unit (which is coupled to the adder units), and a number of clocked storage stages.

REFERENCES:
patent: 6813744 (2004-11-01), Traeber
patent: 7046747 (2006-05-01), Vasquez
patent: 7458008 (2008-11-01), Wang et al.
Xilinx, Inc.,Viterbi Decoder v3.0, DS247 (v1.0), Mar. 28, 2003, pp. 1-24, available from Xilinx, Inc., San Jose, California, USA.
Xilinx, Inc.,Viterbi Decoder v6.2, DS247, Oct. 10, 2007, pp. 1-33, available from Xilinx, Inc., San Jose, California, USA.

Affiliated with

Also associated with

Rating

Method and system for a multi-channel add-compare-select unit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and system for a multi-channel add-compare-select unit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and system for a multi-channel add-compare-select unit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4098669