Method and system for a circuit for timing sensitive...

Details Method and system for a circuit for timing sensitive... Method and system for a circuit for timing sensitive...

2007-08-28

2007-08-28

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S023000

Reexamination Certificate

active

11154765

ABSTRACT:
Systems and methods for circuits with substantially equal propagation delay while providing different drive strengths are disclosed. These systems and methods may allow for a circuit with a drive strength that is some ratio of an arbitrary strength full drive strength circuit. Additionally, these circuits may have substantially the same input capacitance and feedback current as the baseline drive circuit. The input of such a circuit may be coupled to three nodes, one of which is an inverter coupled to the logic to be driven, the second of which is dummy logic, and the third of which is an inverter the output of which is left floating.

REFERENCES:
Weste, Neil H.E. , “Principles of CMOS VLSI Design”, 3rdEd., pp. 218-221, May 11, 2004.

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