Method and structure to reduce defects in integrated...

Details Method and structure to reduce defects in integrated... Method and structure to reduce defects in integrated...

2005-03-01

2005-03-01

Nguyen, Cuong (Department: 2811)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S644000, C438S627000

Reexamination Certificate

active

06861354

ABSTRACT:
A method for forming conductor structures on a semiconductor wafer is provided. The method begins with depositing a seed layer having a substantially consistent thickness over a barrier layer that covers the features and the field regions among them. The process continues with electrodepositing a planar copper layer on the seed layer and subsequently electroetching it until a thinned seed layer remains over the field regions. When another layer of planar copper is deposited on the remaining copper in the features and on the thinned seed layer on the field regions, this structure minimizes stress related defects in the features which occur during a following anneal process.

REFERENCES:
patent: 6342447 (2002-01-01), Hoshino
patent: 6524950 (2003-02-01), Lin
Victoria Shannon, David C. Smith, Novellus Systems Inc., San Jose “Copper Interconnects for High-Volume Manufacturing”Semicondutor International, May 1, 2001.

Affiliated with

Also associated with

Rating

Method and structure to reduce defects in integrated... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and structure to reduce defects in integrated..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and structure to reduce defects in integrated... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3389927