Method and structure to reduce contact resistance on thin...

Details Method and structure to reduce contact resistance on thin... Method and structure to reduce contact resistance on thin...

2008-07-17

2010-11-16

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Total dielectric isolation

C438S583000, C438S508000, C438S508000

Reexamination Certificate

active

07833873

ABSTRACT:
A method (and system) of reducing contact resistance on a silicon-on-insulator device, including controlling a silicide depth in a source-drain region of the device.

REFERENCES:
patent: 5936306 (1999-08-01), Jeng
patent: 6369429 (2002-04-01), Pramanick et al.
patent: 6746926 (2004-06-01), Yu
patent: 6872642 (2005-03-01), Oda et al.
patent: 7531423 (2009-05-01), Cheng et al.
patent: 2006/0281271 (2006-12-01), Brown et al.
patent: 2007/0010051 (2007-01-01), Wu et al.
patent: 2007/0181955 (2007-08-01), Chen et al.
L.T. Su, M. J. Sherony, H.Hu, J.E. Cheung, and D.A. Antoniadis, “Optimization of Series Resistance in Sub-0.2mm SOI MOSFET'S”, IEEE Electron Device Letters, vol. 15, No. 9, Sep. 1994, p. 363-365.

Affiliated with

Also associated with

Rating

Method and structure to reduce contact resistance on thin... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and structure to reduce contact resistance on thin..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and structure to reduce contact resistance on thin... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4190356