Method and structure of column interconnect

Details Method and structure of column interconnect Method and structure of column interconnect

2000-03-17

2002-12-17

Tran, Minh Loan (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

C257S752000, C257S760000

Reexamination Certificate

active

06495917

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor chips and more particularly to structures which protect the chip during bonding processes.
2. Description of the Related Art
The use of low dielectric potential (k) interlevel dielectric (ILD) materials (e.g., spin-on-glass (SOG), Hydrogensilsesquioxane(HSQ), Methylisilane (MSQ), Benzocyclobutene (BCB), etc.) has become very popular for input/output (UO) and mechanical support structures which are applied to a previously fabricated semiconductor chip. Such I/O and support structures are formed after the logical function sections of the semiconductor chip have been completed. Therefore, such structures/processing are sometimes referred to as “back end of line” (BEOL) structures/processing because they are formed at the back end of the production line.
However, many low k materials are brittle or soft as compared to silicon dioxide and, when bonding forces are applied, the low k materials can be easily damaged. More specifically, the forces applied during bonding processes (such as ultrasonic wirebonding) or during the formation of solderball (C
4
) connections, can damage the low k dielectric materials. Thus, the damage from ultrasonic energy (wirebonding), capillary pressure and temperature can weaken or collapse the low k insulator.
Also, ultra low dielectric constant materials (k<3), such as polyarylene ether (trade name SILK manufactured by Dow Chemical, Midland, Michigan, USA, and FLARE manufactured by Honeywell, Sunnyvale, Calif. USA) or silica aerogels, carbon containing CVD dielectrics, Methylsisquoxiane (MSQ), Hydrogen-sisquoxiane (HSQ) have poor mechanical strength as compared to silicon dioxide. Lack of mechanical strength has been a severe problem with connections wirebonded to complimentary metal oxide semiconductors (CMOS) which use ultra w low dielectric constant materials as an intermetal dielectric. Therefore, new processes and structures are needed that will provide compatibility between the low k insulator and the C
4
/wirebond structures.
Current activity with regard to the above problem includes enhancing the material properties of low k dielectrics (such as processes which increase strength and adhesion), integrating multiple metal films on the copper to provide for compatibility with current C
4
/wirebond processes, and silicidation of copper to improve nitride adhesion. A recent publication 1998 IEEE 38th Annual IRPS-Reno, Nev., Mar. 31, 1998, p. 225-231, by Mukul Saran et al. (incorporated herein by reference) describes the use of metal grids to provide for mechanical reinforcement of the dielectric stack to eliminate bond-pad damage during wirebonding of Al or Au wires to aluminum pads.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for a semiconductor chip that includes a plurality of layers of interconnect metallurgy, at least one layer of deformable dielectric material over the interconnect metallurgy, at least one input/output bonding pad, and a support structure that includes a substantially rigid dielectric in a supporting relationship to the pad that avoids crushing the deformable dielectric material.
The support structure includes a cap over the deformable dielectric material, where the cap is co-planer with the patterned last metal layer or the cap has a thickness greater than that of the patterned last metal layer. The support structure may also include patterned metal layers separated by the rigid dielectric where the patterned metal layers are joined by a plurality of metal connections through the rigid dielectric or may include metallic leg structures extending from the last metal layer into the deformable dielectric material. The leg structures can be a plurality of metallic blocks formed at progressive levels within the deformable dielectric material. The metallic blocks can form a herringbone pattern in cross-section or a step-shaped structure in cross-section.
Another embodiment of the invention is an integrated circuit chip that includes logic circuitry, an external insulator covering the logic circuitry, and a contact over the insulator allowing electrical connection to the logic circuitry. The external insulator includes a first dielectric layer having a first dielectric constant and a support structure having a second dielectric constant higher than the first dielectric constant.
Yet another embodiment of the invention is an integrated circuit chip that includes logic circuitry, an external insulator covering the logic circuitry, and a contact over the insulator allowing electrical connection to the logic circuitry. The contact includes a metallic structure extending above the external insulators. The metallic structure has a pillar or pyramid shape.
Yet another embodiment of the invention is an integrated circuit chip that includes logic circuitry, an external insulator covering the logic circuitry, a contact over the insulator allowing electrical contact to the logic circuitry, and a lattice structure that includes a first dielectric having a first dielectric constant and a second dielectric having a second dielectric constant higher than the first dielectric constant. The lattice structure can be a crisscross pattern of the second dielectric in a layer of the first dielectric, an alternating layer of the first dielectric and the second dielectric, or sidewall spacers of the second dielectric between portions of the first dielectric.
Yet another embodiment of the invention is an integrated circuit chip that includes logic circuitry, an external insulator covering the logic circuitry, and a contact over the external insulator allowing electrical contact to the logic circuitry. The external insulator includes support columns between the logic circuitry and the contact. The support columns are portions of metallization and via levels within the external insulator and can be hollow columns filled with an insulator. The support columns can include heat sinks, and are spaced to permit wiring to be positioned within the external insulator.
The invention overcomes the problems associated with conventional BEOL structures that are discussed above. More specifically, the invention comprises additional structures on top of or within the BEOL structure that add support to the inter-layer dielectric (ILD) during wire or C
4
bonding processes.


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patent: 6037668 (2000-03-01), Cave et al.
patent: 6208015 (2001-03-01), Bandyopadhyay et al.
patent: 6222265 (2001-04-01), Akram et al.
patent: 6313537 (2001-11-01), Lee et al.
patent: 63179548 (1988-07-01), None
Planarization of Conductor Surfaces, IBM Technical Disclosure Bulletin, Mar. 1984, vol. 26, No. 10A, p. 4995.
Contactor Lattice for Dislocated C4 Bonds, IBM Technical Disclosure Bulletin, Jul. 1988, vol. 31, No. 2, p. 101-102.
Alternate Chip/Substrate Interconnection Technology, IBM Technical Disclosure Bulletin, Apr. 1992, vol. 34, No. 11, p. 20-21.
Alignment Aid for Stud up Technology, Research Disclosure, Jul. 1989, No. 303, Kenneth Mason Publications Ltd, England.

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