Method and structure for ultra narrow gate

Details Method and structure for ultra narrow gate Method and structure for ultra narrow gate

2006-07-25

2006-07-25

Deo, Duy-Vu N. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S713000, C438S714000, C438S717000, C438S719000

Reexamination Certificate

active

07081413

ABSTRACT:
A method for forming an ultra narrow semiconductive gate structure utilizes a tapered hardmask covered by an oxide liner. The tapered hardmask is formed over the semiconductive gate material by tapered etching. After the tapered hardmask structure is formed over the semiconductive material, an oxide layer is formed over the tapered hardmask. A sequence of highly selective etch operations are carried out to etch uncovered portions of the semiconductive gate material while the portions of the gate material covered by the tapered hardmask and oxide film remain unetched to form ultra narrow gate structures.

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