Method and structure for top-to-bottom I/O nets repair in a...

Semiconductor device manufacturing: process – Repair or restoration

Reexamination Certificate

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C438S015000, C438S016000, C438S017000, C438S108000, C438S613000, C438S434000, C438S343000, C438S142000, C228S180220, C257S048000, C257S737000, C257S738000, C257S778000

Reexamination Certificate

active

06323045

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to repair of defective wiring connections in thin film multi-chip modules or chip carriers, and, more particularly, to the repair of thin film wiring using embedded metallurgy (TSM) repair schemes.
BACKGROUND OF THE INVENTION
The repair of thin film wiring using TSM (Top Surface Metal) repair lines is well known. In the conventional repair process, a defective electrical wiring net, used to connect components on a multichip carrier, is disconnected from its internal wiring through specialized delete locations located at the “C
4
” (Controlled-Collapsed-Chip-Connection) joining, pads. The net is reconstructed with equivalent electrical performance by connecting the X-Y grid of the repair lines on the top surface to the required C
4
pads, matching the timing of the original net.
The reconstruction of the net is normally accomplished by joining the segments of the surface repair lines with individual gold ribbons bonded to the TSM repair lines through a lasersonic bonding methodology. The gold ribbons interconnect specific X and Y repair line segments to rebuild the net topography.
FIG. 1
illustrates a portion of a conventional multi-chip module (MCM) before repair. In
FIG. 1
, C
4
connection
10
is connected to net
12
at via
14
. X repair line
16
and Y repair lines
18
,
20
are part of the top layer. Y repair lines
18
,
20
are connected by Y repair line subway
22
using vias
24
,
26
. Vias
14
,
25
,
26
connect to down levels. C
4
connection
10
has a repair elbow
28
and a bond site
30
.
FIG. 2
is a plan view of the portion of the device shown in
FIG. 1
after the conventional repair process. (
FIG. 3
is a cross-sectional view taken along the line
3

3
of
FIG. 2.
) When a defect is found in net
12
, it is completely disconnected from the circuit using external delete
32
between C
4
connection
10
and via
14
. This process is repeated at every other C
4
connection location for net
12
. To replace this deleted net, a portion of X repair line
16
and Y repair lines
18
,
20
must be used. Conventionally, X repair line
16
and Y repair lines
18
,
20
are cut using deletes. Then, C
4
connection
10
is connected to X repair line
16
using gold ribbon
34
, and X repair line
16
is connected to Y repair line
20
using gold ribbon
36
.
In a multi-layer thin film structure, most of the top-to-top wiring nets, which connect chip C
4
through the thin film layers structure, can be repaired via top surface repair lines. For top-to-bottom nets, which connect C
4
to peripheral I/O, however, there is no established repair methodology. Presently, all I/O repairs are made on a case by case basis, and partial repair and sacrificial repair methods have been employed for some special and simple I/O defects situations. A direct I/O plate-up repair method is a general repair approach, however, the current TF designs do not contain the needed repair features connecting capture pads (C/P) to C
4
pads. The I/O repairability is also a slow and elaborate task, and does not have the manufacturability required for a production line.
A multilayer thin film module is typically processed on the surface of a MLC (Multi-Level Ceramic) carrier. After the structure is built, a full after-thin-film test is performed to confirm the integrity of the thin film structure. At this stage, if a defect is found to be associated with a top-to-bottom I/O net, then the part is in general considered unrepairable and will be rejected. There are some special situations when an I/O defect can be repaired by employing the concept and technique of graphical assisted partial repair. In general, however, there is no systematically established method to repair top-to-bottom I/O nets. The reason for the unrepairability in I/O nets is simply the inaccessibility of the top-to-bottom portion of I/O nets in the thin film on ceramic carrier design structure.
In a typical TF wiring design, about 30% of the capture pads (C/P) and 50% of the C
4
(chip joining sites) are not used. Currently, these unused pads are only filled in by design and have no functionality.
In view of the shortcomings of the prior art, a reliable TF processing alternative is needed to improve the top-to-bottom repair process of thin film products.
SUMMARY OF THE INVENTION
To meet this and other needs, the present invention is directed to a device repair process that uses unused capture pads for top-to-bottom I/O repair. Since there are a substantial number of C
4
and C/P that are not normally used, they can be paired up to form connections from the capture pads at the bottom of the thin film, to the C
4
's at the top of the thin films. In this way, the C/P-C
4
pairing forms z-repair lines in the thin film structure by forming alternative passages from the capture pad to the C
4
.
Of the many unique features of thin film transfer-joining (TFTJ) technology, one of them is top-to-bottom I/O repairability. This z-repair line concept is the foundation for I/O repairability of TF in a TFTJ process. If an I/O net is found defective in the thin film wiring prior to joining to the ceramic carrier, the corresponding capture pad on the ceramic top surface is rewired to a nearby z-repair line site. The connection from the substrate to the capture pad of the defective I/O net is disconnected by means of via blocking or solder ball removal. Since the z-repair line will give the I/O an alternative path to the thin film top surface, a repair of a defective I/O net can be made. The original defective thin film portion of the I/O net is disconnected on the top surface from the C
4
by standard laser delete and then wired to the TSM z-repair feature using conventional repair methodologies. In this way, the I/O net can be repaired via the z-repair lines embedded in the TF structure as part of the design. The solder joining between the ceramic and thin film on the repaired I/O site is preferably removed to eliminate the antenna effect on the remaining TF net.
The key features of this invention are the creation of alternative wiring paths between C
4
's and the bottom surface of the thin film portion of the structure (spare vertical connections), the creation of a simple wiring pattern of X and Y lines on the surface of the ceramic substrate to which the thin film transfer will be mated, and a method to remove or block the solder ball connection from the defective net during joining of the thin film to the ceramic using the solder lamination process.
These and other features and advantages of the invention will become apparent to those skilled in the art upon a review of the following detailed description of the presently preferred embodiments of the invention, viewed in conjunction with the appended drawings.


REFERENCES:
patent: 4304450 (1981-12-01), Bilsback et al.
patent: 4453176 (1984-06-01), Chance et al.
patent: 4817850 (1989-04-01), Wiener-Avnear et al.
patent: 4894708 (1990-01-01), Watari
patent: 5299160 (1994-03-01), Mori
patent: 5493076 (1996-02-01), Levite et al.
patent: 5532853 (1996-07-01), Song et al.
patent: 5725995 (1998-03-01), Leedy
patent: 5841193 (1998-11-01), Eichelberger
patent: 5895230 (1999-04-01), Bartley
patent: 6159657 (2000-12-01), Eichelberger

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