Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1998-10-13
2001-06-19
Chung, Phung M. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S736000
Reexamination Certificate
active
06249889
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a method for testing memories, and more particularly, to a method and structure for testing embedded memories in a large scale or very large scale integrated circuit (VLSI).
BACKGROUND OF THE INVENTION
In recent several years, ASIC (application specific integrated circuit) technology has evolved from a chip-set philosophy to an embedded core based system-on-a-chip (SoC) concept. An SoC IC includes various reusable blocks or cores, such as microcontrollers, interfaces, memory arrays, and DSPs (digital signal processors). Such functional blocks are commonly called “cores”.
FIG. 1
is a schematic diagram showing an example of inner structure of such an SoC IC. In the example of
FIG. 1
, an SoC
10
includes a microprocessor core
11
, a memory core
13
and function specific cores
15
-
17
, a PLL core
18
, and a test access port (TAP)
19
.
Large embedded (on-chip) memories are the key components in SoC ICs. These embedded memories implement register files, FIFOs (first-in-first-out), data-cache, instruction-cache, transmit/receive buffers, storage for texture processing, etc. This invention is directed to a method for testing such embedded (on-chip) memories in an SoC IC. Testing of embedded memories is generally done by one of the following methods:
(1) Direct application of test patterns to an embedded memory under test by an IC tester while accessing the memory through an I/O multiplexing: This method requires modification in the I/Os (input/output) of an SoC by adding a multiplexer therein. Due to this extra multiplexer, there is a permanent penalty, for example, a signal propagation delay, in the performance of the SoC IC. The test patterns are generated by an IC tester's pattern generator such as an ALPG (algorithmic pattern generation) unit. However, due to the multiplexer at the I/Os, the actual test patterns require serialization (parallel to serial conversion) of the ALPG patterns, which increases test complexity, test time and many time losses of at-speed testing.
(2) Test application to an embedded memory under test through local boundary scan or a collar register: This method adds a wrapper (boundary scan or shift-register type wrapper) to an embedded memory to be tested. Thus, the data transfer rate to and from the memory under test slows down by the time equal to the delay of the wrapper. Moreover, during testing, the test patterns are serially shifted-in and response is serially shifted-out. Thus, the test time increases significantly and at-speed testing is not possible.
(3) Memory built-in self-test (BIST): This method requires an additional inner circuit for on-chip test generation and response evaluation. This method is the costliest in terms of hardware overhead (additional chip area). The commercially available memory built-in self-test methods require about 3-4% area overhead for a 16K-bits memory. Also, due to additional circuit parasitic, about 1-2% performance penalty, such as signal propagation delays, occurs in memory read/write operations.
(4) Through ASIC functional test: For some small memory, ASIC vendors include simple write/read operations in the ASIC functional test. Most of the time,
1010
. . .
10
pattern is written and read. Generally, this method is applicable to only small memories and extensive testing is not done by this method.
Because the memory built-in self-test causes very little performance penalty at the chip's I/Os, only about 1-2% penalty in the memory read/write operations and provides an acceptable test time, the memory built-in self-test is increasingly used for embedded memories in system-on-chips. Various types of memory built-in self-test methods are available in the market. However, all the known memory built-in self-test methods are very costly in-terms of hardware overhead and allow only a limited number of memory test algorithms. Another limitation of these methods is that if fault diagnosis is desired, these methods require a significantly large amount of additional hardware to identify the failed bit locations.
As has been foregoing, the conventional test approach using the IC tester or design-for-test scheme is not cost-effective for testing embedded memories in a large scale integrated circuit such as an SoC IC.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to provide a method and structure for testing embedded memories in a large scale integrated circuit (LSI and VLSI), such as a system-on-a-chip (SoC) IC, without requiring any design modification or additional circuit.
It is another object of the present invention to provide a method and structure for testing embedded memories in an SoC IC with no penalty in the performance of the IC.
It is a further object of the present invention to provide a method and structure for testing embedded memories in an SoC IC which allows at-speed testing of embedded memories and facilitates diagnosis.
It is a further object of the present invention to provide a method and structure for testing embedded memories in an SoC IC by providing an assembly language test program which is executed on a microprocessor core in the IC to generates memory test patterns.
It is a further object of the present invention to provide a method and structure for testing embedded memories in an SoC IC with high test efficiency and low cost.
In one aspect of the present invention, the method for testing embedded memories in an integrated circuit having a microprocessor is comprised of the steps of: testing the microprocessor by applying thereto a test pattern and evaluating the resultant output of the microprocessor; applying an object code of an assembly language test program to the microprocessor; generating a memory test pattern by the microprocessor based on the object code of the assembly language test program; applying the memory test pattern to the embedded memory and evaluating the resultant response of the embedded memory by comparing the response with test data applied to the memory.
Another aspect of the present invention is a structure for testing embedded memories. The structure is comprised of: means for testing the microprocessor by applying thereto a random test pattern and evaluating the resultant output of the microprocessor; and a host computer for providing an assembly language test program to the microprocessor through an interface circuit; wherein the embedded memory is provided with a memory test pattern generated by the microprocessor based assembly language test program and the resultant data of the embedded memory is evaluated by the microprocessor.
According to the present invention, no design modification is required and no additional test circuitry is required in the SoC IC. The present invention does not require any design modification in the chip design. There is no performance penalty and the memory is tested at speed. The user can use any memory test algorithm to test embedded memories.
REFERENCES:
patent: 5535164 (1996-07-01), Adams et al.
patent: 5617531 (1997-04-01), Crouch et al.
Rajsuman Rochit
Yamoto Hiroaki
Advantest Corp.
Chung Phung M.
Muramatsu & Associates
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