Method and structure for testing embedded flash memory

Details Method and structure for testing embedded flash memory Method and structure for testing embedded flash memory

2001-04-05

2002-05-28

Zarabian, A. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S185090

Reexamination Certificate

active

06396753

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor memory, and more particular to a method and circuit for testing an embedded flash memory including memory and logic element formed in a single integrated circuit.
BACKGROUND OF THE INVENTION
Advances in the design and fabrication of integrated circuits have resulted in significant decreases in the size of transistors and other components for forming such integrated circuits. Such dramatic increases in the density of components have enabled manufacturers to fabricate high capacity memory devices in the same size substrate previously produced much lower capacity devices. Likewise, for microprocessors and other logic circuits, such increased component density has enabled manufacturers to increase functionality by including additional circuitry on the substrate. In addition to improving functionality and performance of existing types of integrated circuits, a new type of integrated circuit called an “embedded flash memory” in which the logic element and the flash memory (or called EEPROM flash memory) formed in the same integrated circuit is developed. In other words, the logic element is “embedded” in the flash memory.
Referring to
FIG. 1
, a block diagram of embedded flash memory in the prior art. In the embedded flash memory
100
, a flash memory array
110
and a logic element
120
are formed in the same semiconductor substrate. The logic element
120
is connected to the memory array
110
through an address pin
112
, control pin
114
and data pin
116
, and control address, control and data signal on these respective pins to transfer data to and from the memory array
110
.
There are numerous performance benefits from the embedded flash memory of which the memory array
110
and the logic element
120
are formed in the same semiconductor substrate. The bandwidth of the memory array
110
can be substantially increased by increasing the width of data pin
116
to transfer more data during each access action of the memory array
110
. Moreover, the embedded flash memory
100
has additional advantages of lower power consumption and lower electromagnetic radiation than the conventional flash memory.
During the manufacture of the embedded flash memory
100
, the embedded flash memory
100
needs to be tested just as with conventional flash memory. However, testing the embedded flash memory presents new problems not encountered in conventional flash memories. As shown in
FIG. 1
, a test system
200
is generally connected to the logic element
120
through an external terminal
130
of the logic element
120
to transfer test address, control and data signal for accessing data of the memory array
110
. The transferred test signals to the memory array
110
must transmit through the logic element
120
first, and the output data signals also must pass the logic element
120
and then to the test system
200
. Therefore, the actual access time is total access time passing though the logic element
120
, not an access time of memory array
110
.
In order to dominate actual access time of the memory array of the Embedded flash memory to overlook whether achieving predetermined operation performance, there is a need for testing the access time of the memory array.
SUMMARY OF THE INVENTION
Therefore, the present invention provides a method for testing memory array in an embedded flash memory including a memory array and a logic element, and the memory array connected to a test system through the logic element, comprising:
a) testing the memory array to obtain an original access time;
b) gating an output signal from the memory array to the test system by a speed control pin after a first test time and detecting the output signal with the test system;
c) if the test system detecting the output signal, iterating the step (b) with a second test time; and
d) obtaining a memory array access time if the test system detecting the output signal in step (c).
The present invention also provides a gating circuit for testing a memory array in an embedded flash memory including a memory array and a logic element. The memory array is connected to a test system through the logic element. The gating circuit comprises a control transistor connected between a sense amplifier and an I/O buffer, and a speed control pin connected between the logic element and a gate terminal of the control transistor to gate an output signal from the memory array to the test system by switching the control transistor on or off. The control transistor may be a NMOS transistor, PMOS transistor, depletion mode NMOS transistor or depletion mode PMOS transistor.
By gating the output signal from the memory array to the logic element during shortening test time for test system step by step, the output signal is detected to obtain the memory array access time conveniently and precisely.


REFERENCES:
patent: 5930188 (1999-07-01), Roohparvar
patent: 6243307 (2001-06-01), Kawagoe

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