Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-07-22
2001-04-10
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S629000, C438S636000, C438S786000
Reexamination Certificate
active
06214721
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the manufacture of integrated circuit structures. In particular, the invention relates to suppressing light reflections from an integrated circuit structure during photolithography exposure steps by including wave dampening material in the structure. The techniques of the invention are applicable to both single and dual damascene processes.
2. Discussion of the Related Art
In semiconductor integrated circuit processing, it is common to use a layer of material to suppress reflections from underlying surfaces during photolithography exposure steps. This layer is known an the antireflective coating or ARC. It is desirable to suppress reflections from underlying layers so that the photoresist is not exposed to the reflected light waves which leads to variation in critical dimensions.
The ARC thickness is selected such that the light waves that are reflected off the underlying surface are 180 degrees out of phase with the light waves that are reflected off the top surface of the ARC. In this way, destructive interference occurs and the reflection is suppressed. This is shown in FIG.
1
.
The total distance that a light wave travels is determined by the thickness of the material that it passes through. Unfortunately, due to process variations and the effects of processing, the thickness of the materials may vary substantially over time. If the thickness of the materials through which the reflected light must pass does vary, then the light waves that are reflected from the bottom material will not be exactly 180 degrees out of phase with the light waves that are reflected off the ARC. In this case, only partial destructive interference occurs and some of the reflected light waves escape and double expose the photoresist.
This problem of varying thickness becomes worse when materials which are transparent to the wavelength of light used during photolithographic exposure are used in the process architecture. An example of this is during processing of a copper dual damascene film stack. This is shown in FIG.
2
. In this case, some of the materials under the ARC may be silicon dioxide, silicon nitride or low k dielectrics that are largely transparent to the incoming light. Other materials under the ARC, such as copper metal, reflect the incoming light in varying amounts. The reflection from underlying materials may occur off different metal layers or off the silicon substrate. Thus, the light waves must travel a considerable distance through materials which may vary in thickness from the desired amount by hundreds or thousands of Angstroms due to normal process variations. Thickness variations of this amount render the top ARC layer ineffective for destructive interference.
SUMMARY OF THE INVENTION
An embodiment of the present invention provides one or more “built-in” wave dampening, antireflective thin-film layers in a copper dual damascene film stack. The wave dampening layers reduce the standing wave intensity in the deep-UV photoresist. This is accomplished by depositing optically customized silicon/oxide
itride films during dual damascene processing. In particular, one or more of the silicon nitride layers utilized in conventional dual damascene processing are replaced with a light absorbing silicon oxynitride film to provide built-in dampening layers. The silicon oxynitride stack can be densified by heat treatments to minimize electrical leakage concerns, if any. The invention eliminates the need for adding extra thin-film stacks during deep-UV photoprocessing.
A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized.
REFERENCES:
patent: 5525542 (1996-06-01), Maniar et al.
patent: 5639687 (1997-06-01), Roman et al.
patent: 5668052 (1997-09-01), Matsumoto et al.
patent: 6017815 (2000-01-01), Wu
patent: 6025259 (2000-02-01), Yu et al.
patent: 6037276 (2000-03-01), Lin et al.
patent: 6060380 (2000-05-01), Subramanian et al.
Bendik, Jr. Joseph J.
Perry Jeffrey R.
National Semiconductor Corp.
Quach T. N.
Stallman & Pollock, llp
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