Method and structure for stacked DRAM capacitors and FETs...

Details Method and structure for stacked DRAM capacitors and FETs... Method and structure for stacked DRAM capacitors and FETs...

2002-01-14

2003-03-25

Nelms, David (Department: 2818)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C438S241000

Reexamination Certificate

active

06538287

ABSTRACT:

BACKGROUND OF THE INVENTION
(1) Field of the Invention
This invention relates to semiconductor integrated circuit devices, and more particularly to a structure and method for integrating logic and dynamic random access memory (DRAM) cells. The process is particularly useful for integrating (embedding) high-density memory with logic circuits on the same chip while reducing the processing steps and minimizing thermal cycles that can degrade the logic devices. This is achieved by using a single thin high dielectric layer to form concurrently the field effect transistor (FET) gate oxide and the DRAM stacked capacitor interelectrode dielectric layer.
(2) Description of the Prior Art
Integrated logic and DRAM structures are becoming increasingly important for future product applications. However, the current processing is becoming more difficult and the structures are becoming more complex. In these advanced circuits the logic FETs require shallower diffused junctions and thinner gate oxides to increase performance, while the decreasing size of the DRAM capacitors requires increased capacitance for maintaining an acceptable charge level. Besides the increasing process complexity, an important issue is that the shallow FET logic devices degrade because of the thermal cycles used during the later fabrication of the DRAM capacitors. This problem is best understood with reference to the schematic cross-sectional view of a conventional device having merged high-density memory/logic circuits, as shown in FIG.
1
. The portion of the drawing in the left part of
FIG. 1
is for the memory and labeled DRAM, while the right side depicts the logic portion. In this approach the N- and P-doped wells
16
and
26
, respectively, are formed first in the substrate
10
. An N-doped deep well
14
is also formed in the memory area at this time. The field oxide
12
, such as a shallow trench isolation is formed next to electrically isolate device areas. The FETs are formed next by growing a gate oxide
27
. A polycide layer
31
is deposited and patterned to form the FET gate electrodes
31
. In the conventional process, lightly doped source/drains
17
(N
−
) are implanted adjacent to the gate electrodes
31
. Sidewall spacer
33
are formed by depositing and etching back an insulator. The heavily doped source/drain contact areas
19
(N
+
) are formed next by ion implantation. An insulating layer
35
is deposited on which the bit lines
37
are formed, then a second insulating layer
39
is deposited on which is formed the DRAM stacked capacitors
41
(layers
41
A,
41
B, and
41
C). An insulating layer
47
is deposited to electrically insulate the capacitors, and a multilevel of metal interconnections
45
,
49
, and
53
is formed with interposing insulating layers
47
, and
51
, and an upper passivation layer
55
to wire up the chip, as shown for the DRAM region in the left portion of FIG.
1
and for the logic region in the right portion.
Unfortunately, in future advanced FET devices, it is necessary to maintain very thin gate oxides and shallow diffused source/drain areas to achieve the necessary performance (switching speeds). The numerous thermal processing cycles (steps) required to form the bit lines and DRAM stacked capacitors preclude the possibility of making FETs with shallow diffused source/drain junctions.
Several methods for making improved embedded or merged DRAM circuits have been reported in the literature. One method for making DRAM capacitors with increased electrode area is described in U.S. Pat. No. 5,821,139 to Tseng. In this method the capacitors are made after the FETs, and therefore cannot circumvent the above problem of excessive thermal cycles. In U.S. Pat. No. 6,015,732 to Williamson et al., a method is described for making a dual gate oxide for integrated circuits. One of the gate oxides also serves as a capacitor interelectrode dielectric layer. However, the capacitor is formed on an insulating layer for I/O applications and Williamson does not describe or address the need for making DRAM capacitors with node contacts on the substrate.
However, there is still a need in the semiconductor industry to provide a cost-effective manufacturing process for making logic circuits with embedded DRAM devices while reducing the thermal cycles for the advanced FETs so as to achieve shallow diffused source/drain junctions required for high-performance circuits.
SUMMARY OF THE INVENTION
It is a principal object of the present invention to make logic circuits with embedded DRAM cells using fewer processing steps.
It is another object of the present invention to achieve the above objective to form the DRAM capacitor prior to forming the logic and DRAM FETs source/drain diffusion, and to thereby minimize the number of thermal cycles that the shallow diffused FETs-would be subjected to. This prevents the electrical degradation of the FETs.
Still another object of this invention is to use a single high-dielectric-constant layer as the FET gate oxide to increase logic FET performance and concurrently to increase the charge storage on the stacked DRAM capacitor while reducing the number of process steps.
The method for achieving the above objectives for these improved embedded DRAM/logic circuits starts by providing a semiconductor substrate. Typically the substrate is a P
−
doped single-crystal silicon having a <100> crystallographic orientation. A field oxide is formed using shallow trench isolation (STI) to surround and electrically isolate device areas in logic regions and DRAM regions on the substrate. P-doped wells and deep N-doped wells are formed in the memory region device areas by ion implantation. An etch-stop layer, composed of silicon nitride (Si
3
N
4
), is deposited by chemical vapor deposition (CVD) and a disposable first insulating layer composed of CVD silicon oxide (SiO
2
) is deposited. First contact openings are etched in the first insulating layer and the etch-stop layer to the device areas in the memory regions. Capacitor bottom electrodes are formed in the first openings by depositing a conformal first polysilicon layer and chemically-mechanically polished back to the surface of the first insulating layer. The first insulating layer is selectively removed to the etch-stop layer using a wet etch (i.e., hydrofluoric acid), leaving free-standing cylindrical-shaped capacitor bottom electrodes. The area of the capacitor and therefore the capacitance is determined by the thickness of the first insulating layer. Next the etch-stop layer is selectively removed from the substrate surface using, for example, a phosphoric acid etching solution. N-doped wells and P-doped wells are then implanted in the device areas of the logic regions and include the antipunchthrough implants. A key feature of this invention is to deposit a conformal dielectric layer to form the gate oxide for the FETs and concurrently to form an interelectrode dielectric layer on the capacitor bottom electrodes. The preferred interelectrode dielectric layer is a silicon oxynitride, tantalum pentoxide, and the like. Next a conformal second polysilicon layer is deposited. The second polysilicon layer is then doped by ion implantation. An additional implant mask and an ion implantation can be used to selectively dope the second polysilicon in the DRAM cell array regions. The second polysilicon layer is patterned to form FET gate electrodes and to define the capacitor top electrodes over the DRAM capacitor bottom electrodes. Lightly doped source/drain areas for the FETs are formed adjacent to the gate electrodes by ion implantation. Sidewall spacers are formed on the sidewalls on the gate electrodes by depositing a conformal insulating layer and anisotropically etching back to the top surface of the patterned second polysilicon layer. Then the FET source/drain contact areas are formed by ion implanting a dopant adjacent to the sidewall spacers. To reduce resistance and to improve electrical conductivity a salicide process is used. The salicide is formed by depositing a refractory metal,

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