Method and structure for shallow trench isolation

Details Method and structure for shallow trench isolation Method and structure for shallow trench isolation

1999-10-19

2002-10-29

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Introduction of conductivity modifying dopant into...

Ion implantation of dopant into semiconductor region

C438S433000, C438S527000, C438S224000

Reexamination Certificate

active

06472301

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally semiconductor devices and more particularly a method and structure for shallow trench isolation.
BACKGROUND OF THE INVENTION
Isolation between devices within a semiconductor chip becomes more critical as device size gets smaller. Field oxide isolation is one common solution. With field oxide isolation, regions of oxide material are thermally grown to define active areas on the semiconductor chip. This technique requires considerable surface area and therefore is not desirable for highly integrated devices.
Another known solution is deep trench isolation, a technique where relatively deep trenches are filled with dielectric material and positioned between active devices. Unfortunately, forming reliable deep trenches is very complicated and challenging, especially as spacing between devices get smaller. In addition, acceptable isolation is often not possible unless the depth of the trench is larger than the well depth.
Hence, shallow trench isolation (STI) is often used. One problem with STI is caused by poor well alignment, a situation where the boundary of the well is at the edge or at the outside of the trench.
Poor well alignment is not typically due to poor lithography and process control. Rather, it is often due to different well dopant concentration and diffusion. Well dopant diffusion is a difficult to adjust to achieve good well alignment since dopant diffusion is determined by the dopant species, dose, and profile and these parameters are governed by device performance optimization. As a result, it is very difficult to adjust the well implant conditions to achieve the good well alignment without compromising the device's performance.
The present invention provides an isolation process which solves some of the problems found with the prior art.
SUMMARY OF THE INVENTION
In various aspects of the present invention, additional implants through a shallow trench are used to achieve good isolation without impacting device performance. The new process is very simple and highly compatible with current CMOS processes.
In this disclose, an implant, preferably low dose, through STI is used to achieve good well alignment. This implant gives device designers a new knob to optimize device performance and isolation simultaneously.
In one embodiment of the present invention, a trench is formed in a semiconductor body. A dielectric layer is formed within the trench. Dielectric layer lines the sidewall and bottom portions of the trench in a manner where the thickness of the dielectric at the sidewall is greater than the thickness of the dielectric at the bottom. A dopant can be implanted into the semiconductor body beneath the trench.
In one aspect, the present invention solves device isolation problem by using a simple implant. This invention provides a knob to allow device designer to optimize device performance and isolation simultaneously. The usage of a nitrogen implant and an implant spacer (dielectric layer) before the implant effectively reduces the unwanted diffusion and distribution of the implanted dopant. Therefore, this technique has no significant impact on device performance.


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