Method and structure for reducing the effect of vertical...

Details Method and structure for reducing the effect of vertical... Method and structure for reducing the effect of vertical...

2006-01-20

2009-06-09

Sarkar, Asok K (Department: 2891)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S584000, C257S758000, C257SE21017

Reexamination Certificate

active

07544612

ABSTRACT:
According to an exemplary embodiment, a method for fabricating a multilayer semiconductor structure includes forming first and second patterned segments, where a first patterned segment sidewall is separated from a second patterned segment sidewall by a first gap; forming a first conformal layer over first and second patterned segments and first gap, where the first conformal layer forms a depression over the first gap; forming a third patterned segment in the depression such that a third patterned segment sidewall is separated from the first patterned segment sidewall by a distance, where the third patterned segment sidewall is separated from a depression sidewall by a second gap; and forming a second conformal layer over the first conformal layer, third patterned segment, and second gap, where a dip is formed in the second conformal layer over the second gap. The distance is controlled so as to reduce a size of the dip.

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patent: 7235865 (2007-06-01), Juengling
Oguier-Monnier et al. “Reliability Improvement of EEPROm by using WSI@ polycide gate”, Microelectronics Reliablity 39 (1999), pp. 897-901.

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