Method and structure for reducing noise in output buffer circuit

Details Method and structure for reducing noise in output buffer circuit Method and structure for reducing noise in output buffer circuit

1994-12-20

1996-05-14

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

326 83, 326 87, H03K 1716

Patent

active

055171303

ABSTRACT:
A method and structure for controlling ground bounce and power supply noise during switching is provided in which a plurality of pull-up and/or pull-down transistors are provided whose turn on during switching is controlled in order to provide the desired slew rate in order to control the deleterious effects of ground bounce and power supply noise. In one embodiment, a plurality of pass transistors are used in order to delay a logical signal in order to control the slew rate. In one embodiment, these pass transistors are sensitive to ground bounce, providing a positive feedback mechanism to further enhance the control of ground bounce. In one embodiment, an RC network is conveniently formed in order to control slew rate, and in one embodiment the RC network is sensitive to ground bounce, providing positive feedback in order to further control the slew rate as a result of detected ground bounce.

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