Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having air-gap dielectric
Reexamination Certificate
1996-12-30
2001-10-16
Lee, Eddie (Department: 2815)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having air-gap dielectric
C438S411000, C438S421000, C438S619000, C438S631000, C438S778000, C257S758000
Reexamination Certificate
active
06303464
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit devices, and in particular, to the design of reduced capacitance interconnection systems for semiconductor integrated circuit devices.
2. Description of Related Art
Interconnect system design for modern integrated circuit devices, especially for microprocessors, involves many considerations to minimize noise, ensure proper signal timing and switching, and to optimize performance. This is especially true as interconnect density increases and the interconnect system becomes a performance limiting factor. The trend towards smaller, lower power devices, for example, requires interconnect system capacitance to be reduced as much as possible in order to minimize effects such as resistor/capacitor (RC) delay and cross-talk on signals transmitted by the interconnect system, which may be exacerbated by the reduced spacing between interconnect lines.
The capacitance of an interconnect system is essentially equivalent to the cumulative total of the capacitance experienced by each interconnect line in the interconnect system. The capacitance experienced by a particular interconnect line, referred to herein as the line capacitance, includes both line-to-line capacitance components (between adjacent lines on a same metal layer) and line-to-next metal layer components (between an interconnect line and metal layer(s) above and/or below the interconnect line).
Neither the surface area of the interconnect lines nor the spacing between interconnect lines or metal layers can be easily changed without affecting other critical parameters such as the packing density of the integrated circuit or the resistance of the interconnect lines. Thus, the focus in reducing the capacitance of interconnect systems is on reducing the effective dielectric constant of the material between the interconnect lines to a value below that of SiO
2
, one of the most commonly used interlevel dielectric (ILD) materials.
There are many requirements for an ILD material to be viable for use in modern integrated circuit chips. Mechanical strength and stability, long term reliability, ability to withstand semiconductor processing conditions and cost considerations are key among these factors. Many materials having low dielectric constants have been evaluated and found to be unacceptable for use as ILD materials based on one or more of the above criteria. For example, some organic polymers which have dielectric constants lower than the dielectric constant of SiO
2
are mechanically weak and may not be able to withstand the high temperatures and mechanical stresses to which the interconnect system is subjected during processing and prolonged use. Further, many materials with lower dielectric constants do not have the heat conduction properties of SiO
2
which are important for higher density integrated circuits.
Different processing approaches, such as the creation of “air bridges” have also been used in an attempt to reduce the effective dielectric constant of the material between interconnect lines. One approach to forming air bridges is described in U.S. Pat. No. 5,324,683 to Fitch et al. In Fitch, air regions are formed by selectively removing either a sacrificial spacer or a sacrificial layer. While air has a much lower dielectric constant than SiO
2
, the air bridge approach requires additional processing steps and, because the air bridges typically include a relatively large area of material unsupported by an underlying structure, may lack the mechanical strength required for a sufficiently robust interconnect system for modern integrated circuits.
Thus, what is needed is a lower capacitance interconnect system which is mechanically strong and stable, is not vulnerable to particular steps in the semiconductor fabrication process, and is cost-effective to implement.
SUMMARY OF THE INVENTION
The invention provides a reduced capacitance interconnect system for use in integrated circuits. The interconnect system of the invention is formed on an integrated circuit including a semiconductor substrate and a first dielectric layer formed on the semiconductor substrate. A first metal layer including multiple interconnect lines is formed on the first dielectric layer to a predetermined level above the first dielectric layer. Each of the multiple interconnect lines is separated from each adjacent interconnect line by a trench including a trench having a highest aspect ratio. A second dielectric layer is formed on the first metal interconnect layer and in the trenches between interconnect lines such that an enclosed void having a void tip substantially level with the top of the metal layer is formed in at least each trench having an aspect ratio above a predetermined minimum aspect ratio, wherein the enclosed void in the trench having the highest aspect ratio has a void volume which is at least 15% of the volume of the trench.
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Chiang Chien
Fraser David B.
Gaw Eng T.
Marieb Thomas N. D.
Vu Quat T.
Díaz Jose′ R
Faatz Cynthia T.
Intel Corporation
Lee Eddie
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