Radiant energy – Irradiation of objects or material – Irradiation of semiconductor devices
Reexamination Certificate
2002-10-29
2004-10-05
Lee, John R. (Department: 2881)
Radiant energy
Irradiation of objects or material
Irradiation of semiconductor devices
C250S310000, C250S311000, C250S307000, C250S306000
Reexamination Certificate
active
06800864
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to making of masks for semiconductor use and more particularly to calibration of an electron beam tool used in writing to a substrate.
BACKGROUND OF THE INVENTION
In today's fabrication of Integrated Circuits (IC) and other semiconductor devices, lithographic delineation procedures are used to yield positive or negative images to bring about selective processing, e.g. etching, implantation, diffusion, deposition, etc. This is especially true in fabrications of masks where the fabrication tool provides Blocking regions and Transparent regions which when illuminated by electron radiation yields an image defined by relatively low and high electron intensities, respectively. A Blocking region is usually defined as the mask region resulting in a degree of electron attenuation in the image which is of consequence in device fabrication. By contrast, a Transparent region is the mask region resulting in a degree of electron attenuation in the image which is small relative to blocking regions in terms of device fabrication. In the semiconductor industry, there is a continuing trend toward an increased device density. To achieve this, there is a continued effort towards the scaling down of device dimensions on semiconductor wafers. As smaller feature sizes become the new requirements (i.e. decreased width and spacing of interconnecting lines, etc.), new ways have to be utilized to achieve their manufacturing. High resolution lithographic processes are used as one of these manufacturing techniques to yield small component features.
In general, lithography refers to processes for pattern transfer between various media. In lithography for integrated circuit fabrication, a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film, the resist. The film is then selectively exposed to radiation, such as optical light, x-rays, or an electron beam, through an intervening master template or the mask, forming a particular pattern. (In a mask, this leads to the creation of Blocking and Transparent regions which when illuminated by electron radiation yields an image defined by relatively low and high electron intensities, respectively.)
Most often exposed areas of the coating become either more or less soluble than the unexposed areas (depending on the type of coating) in a particular solvent developer. The more soluble areas are removed with the developer in a developing step, the less soluble areas remain on the silicon wafer forming a patterned coating. The pattern corresponds to the image of the mask or its negative. The patterned resist is used in further processing of the silicon wafer.
At various stages in forming the patterned resist coating and processing the silicon wafer, it is desirable to measure critical dimensions resulting from the lithographic process. Critical dimensions can include the size of features in the wafer or patterned resist such as line widths, line spacing, and contact dimensions. Several calibration methods are developed and can be used such as scanning electron microscopy (SEM) systems.
In such calibration system, because of the super fine structures to be calibrated, an electron beam is often scanned across the sample. The beam interacts with the sample to produce measurable responses that vary with position over the course of a scan. Although all such calibration systems measure critical dimensions with high precision, they must be calibrated frequently for the measurements to be accurate. Precise measurements are reproducible, but contain systematic errors that must be quantified and taken into account for the measurements to be accurate. Calibration quantifies systematic errors and is carried out on a regular basis.
Calibration involves taking measurements on a calibration standard. A calibration standard is a sample having accurately known dimensions. One calibration standard commonly employed is a periodic pattern formed into a silicon substrate. Another type of calibration standard is formed with a patterned polysilicon coating over a silicon wafer. A thin layer of silicon oxide is used to facilitate binding between the patterned polysilicon and the wafer. A similar calibration standard is formed with a uniform polysilicon coating over the silicon oxide layer and has a calibration patterned formed in another silicon oxide coating that is formed over the polysilicon. Other calibration standards are also used and are available.
A number of problems, however, still exists in the fabrication of masks and calibration of such devices using (E beam) tools. One of the biggest problems is the presence of detractors such as noise and frequency both in the calibration stage and the actual usage of the tool. Therefore, an improved structure and method is needed to eradicate or at least reduce the presence of such detractors in the calibration and usage of E beam tools in conjunction with the fabrication of semiconductor devices.
SUMMARY OF THE INVENTION
These and other objects are provided by the present invention for an apparatus and method for reducing noise and resonance detractors connected with an E beam tool. The invention provides a plurality of embodiments. In one embodiment, the E beam tool will be calibrated and the results will be then filtered to counter the effects of the noise afterwards. The corrections could be filtered by averaging the corrections over a subfield, and applying Fast Fourier Transform (FFT) to the set of averaged subfield corrections which will then be zero padded to the nearest power of 2. Knowing the frequency bands where the peaks may exist, the peaks can be removed in small neighborhood of each resonance or in a band of frequencies or both. Both linear and nonlinear filtering techniques may be used. An inverse FFT will then be performed (if FFT function applied originally) to adjust the corrections with the results.
In an alternate embodiment of the present invention, a filter is applied in the actual feedback of the E beam tool for the writing cycle. First the raw feedback data over each subfield is averaged and then the result is padded to nearest power of two. An FFT is then applied and the resonance or noise areas are removed by using a filter. The average feedback is then reconstructed through the application of an inverse FFT to adjust the corrections with the results. Again as before, both linear and nonlinear filters are equally applicable.
REFERENCES:
patent: 5591971 (1997-01-01), Shahar et al.
patent: 5621656 (1997-04-01), Langley
Anderson Jay H.
International Business Machines - Corporation
Lee John R.
Leybourne James J.
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