Method and structure for performing pipeline burst accesses in a

Details Method and structure for performing pipeline burst accesses in a Method and structure for performing pipeline burst accesses in a

1996-07-15

1998-07-21

Swann, Tod R.

Electrical computers and digital processing systems: memory

Storage accessing and control

Access timing

36518905, G11C 700

Patent

active

057847053

ABSTRACT:
A method and structure for implementing pipeline burst read and write operations in a semiconductor memory having a memory cycle time substantially longer than its I/O data cycle-time. The memory system includes a read buffer which stores all data required for a read burst transaction. All read burst data is loaded from the memory to the read buffer at the beginning of each burst read access. The memory is then isolated from the read buffer and prepared to perform the next burst access. During this time, the read data values are provided to the I/O device from the read buffer. A double-buffering technique provides gap-less output data for consecutive pipeline-burst read transactions. The memory system uses a two-entry write buffer in a first in, first out manner for pipeline-burst write operations. Each write buffer entry stores data for an entire burst transaction and a corresponding address. The first entry stores the data and address for a current write transaction and the second entry stores the data and address for a previous write transaction. The first and second entries are isolated to allow the second entry to provide its data and address to the memory while the first entry stores its corresponding data and address. A high-bandwidth transfer rate between the second entry and the memory with time to prepare the memory for the next transaction.

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