Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2006-10-17
2006-10-17
Nguyen, T (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S141000, C711S145000
Reexamination Certificate
active
07124254
ABSTRACT:
A method and structure for equipping a cache with information to enable the processor to track and report whether a given speculative access causes prefetches and/or pollutions of the cache. Two types of events are tracked in one of two different ways: first by counting/tracking prefetch operations, either globally or on a per instruction address basis and then by counting/tracking cache pollutions, either globally or on a per instruction address basis.
REFERENCES:
patent: 6438673 (2002-08-01), Jourdan et al.
patent: 6725338 (2004-04-01), Gomez et al.
patent: 7010648 (2006-03-01), Kadambi et al.
patent: 7051192 (2006-05-01), Chaudhry et al.
Abraham Santosh G.
Fahs Brian M.
Nair Sreekumar
Gunnison McKay & Hodgson, L.L.P.
McKay Philip J.
Nguyen T
Sun Microsystems Inc.
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