Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step
Reexamination Certificate
2005-06-07
2005-06-07
Whitehead, Jr., Carl (Department: 2813)
Semiconductor device manufacturing: process
Packaging or treatment of packaged semiconductor
Including adhesive bonding step
C438S125000, C257S701000
Reexamination Certificate
active
06902956
ABSTRACT:
A semiconductor package structure for a ball grid array type package using a plurality of pieces of adhesive elastomer film to attach a semiconductor die to a substrate having conductive traces in order to alleviate thermal mismatch stress between the semiconductor die and the printed circuit board to which the packaged device is soldered, while maintaining the reliability of the packaged device itself.
REFERENCES:
patent: 4796078 (1989-01-01), Phelps, Jr. et al.
patent: 5019535 (1991-05-01), Wojnarowski et al.
patent: 5122858 (1992-06-01), Mahulikar et al.
patent: 5277972 (1994-01-01), Sakumoto et al.
patent: 5304842 (1994-04-01), Farnworth et al.
patent: 5461087 (1995-10-01), Takahashi et al.
patent: 5461255 (1995-10-01), Chan et al.
patent: 5656551 (1997-08-01), Corbett et al.
patent: 5773113 (1998-06-01), Akhter
patent: 5824182 (1998-10-01), Sakumoto et al.
patent: 5840598 (1998-11-01), Grigg et al.
patent: 5852326 (1998-12-01), Khandros et al.
patent: 5866949 (1999-02-01), Schueller
patent: 5874784 (1999-02-01), Aoki et al.
patent: 5891566 (1999-04-01), Sakumoto et al.
patent: 5943557 (1999-08-01), Moden
patent: 5960260 (1999-09-01), Umehara et al.
patent: 6002167 (1999-12-01), Hatano et al.
patent: 6107679 (2000-08-01), Noguchi
patent: 6169328 (2001-01-01), Mitchell et al.
patent: 6294040 (2001-09-01), Raab et al.
patent: 6359334 (2002-03-01), Jiang
patent: 1-244652 (1989-09-01), None
patent: 2-105443 (1990-04-01), None
patent: 4-199723 (1992-07-01), None
“ALT Leadframe Adhesive Tapes, Technical Information and Comparative Data,”Brady,http://www.unit.ru/marking/alt.htm, pp. 1-7 (Feb. 23, 1999).
Electronic Packaging and Interconnection Handbook,New York, McGraw-Hill, Inc., pp. 2.2-2.7.
Berezny Nema
Dorsey & Whitney LLP
Jr. Carl Whitehead
Micro)n Technology, Inc.
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