Electrical computers and digital processing systems: support – Clock – pulse – or timing signal generation or analysis – Counting – scheduling – or event timing
Reexamination Certificate
2000-09-06
2003-12-02
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Clock, pulse, or timing signal generation or analysis
Counting, scheduling, or event timing
C714S001000, C714S025000, C714S047300
Reexamination Certificate
active
06658584
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to a method and structure for managing large counter arrays and, more particularly, to coprocessors and their use by counter managers for managing large counter arrays. In even more particular aspects, this invention relates to managing the counting of a large number of individual events in a computer network system where large volumes of information are being passed, such as, for example, in a communications network wherein at times there are a large number of packets of information containing a great number of bits being passed in a very short period of time from multiple input ports to multiple output ports.
2. Background Art
While the invention is not so limited, it is especially useful in communication network systems where large volumes of frames or packets of information are passed from port to port and it is necessary to statistically evaluate the system based on the traffic volume through each port and with the traffic volume between various ports, the number of packets of various sizes of information which are delivered or discarded and other information relating to the operation of the network system. One particular network system of this type is shown and described in U.S. patent application Ser. No. 09/544,896, filed Apr. 7, 2000, entitled Network Processor/Software Control Architecture, the contents of which are incorporated herein by reference as if they were fully set forth. In this type of system, data frames are received at one port from an external source such as a computer, processed and delivered from the incoming port to the required destination port. These incoming ports and destination ports may be on the same blades or different blades and the various statistical information such as that noted above needs to be accumulated. One technique for accumulating the statistical information is to count the number of occurrences of the various events, such as data entry through a specific port, data exit through a specific port, traffic between specific ports, discarded data the size of the frames, and other characteristics of the data and store each of these counts in some type of memory.
Prior art techniques for storing such information utilize the internal processors within the communication system to manage the counting of events. This imposes a significant additional burden on the processors within the system, making the system less efficient than it could be if this task were not required of the internal processors.
SUMMARY OF THE INVENTION
According to the present invention, a method and structure for counting and storing the number of occurrences of each of a plurality of events occurring in a processor complex, which processor complex has at least one processor which processes multiple groups of data in a multiplicity of ways, is provided. The structure includes multiple storage devices, each of which includes a plurality of arrays of memory storage for storing count information of each event, which arrays are divided into a plurality of separately addressable groups of memory addresses in each memory array. At least one counter element is associated with each array of memory. A table is provided which contains information, including a point of reference in each array to uniquely define the structure and location of each memory array. At least one processor generates a plurality of parameters for each of the events to uniquely identify the event. A counter manager is provided which communicates with said at least one processor through its associated coprocessors and receives the parameters of each event generated from the at least one processor. The counter manager, utilizing the table and the parameters information from the at least one processor determines the unique physical address location associated with the event, reads the data from the unique address, modifies the read data according to the instructions and writes the modified data to the determined address. The invention also contemplates reading the information which has been stored for statistical evaluation at the address without modifying the stored information.
REFERENCES:
patent: 5414704 (1995-05-01), Spinney
patent: 5446560 (1995-08-01), Schwartz
patent: 5471640 (1995-11-01), McBride
patent: 5615135 (1997-03-01), Waclawsky et al.
patent: 5687173 (1997-11-01), Melden et al.
patent: 5784554 (1998-07-01), Hsiung
patent: 5790625 (1998-08-01), Arimilli
patent: 5991708 (1999-11-01), Levine et al.
patent: 6052708 (2000-04-01), Flynn et al.
patent: 6360337 (2002-03-01), Zak et al.
patent: 6519330 (2003-02-01), Goto et al.
Bass Brian Mitchell
Davis Gordon Taylor
Heddes Marco C.
Driggs, Lucas, Brubaker & Hogg
International Business Machines - Corporation
Lee Thomas
Nieves Michael
LandOfFree
Method and structure for managing large counter arrays does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and structure for managing large counter arrays, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and structure for managing large counter arrays will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3181551