Method and structure for low-k interlayer dielectric layer

Details Method and structure for low-k interlayer dielectric layer Method and structure for low-k interlayer dielectric layer

2008-07-11

2010-10-05

Smoot, Stephen W (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S624000, C438S637000, C257SE21581

Reexamination Certificate

active

07807564

ABSTRACT:
An integrated circuit interconnect structure. The structure includes a substrate and a layer of transistor elements overlying the substrate. A first interlayer dielectric layer is formed overlying the layer of transistor elements. An etch stop layer is formed overlying the first interlayer dielectric layer. A contact structure including metallization is within the first interlayer dielectric layer and a metal layer is coupled to the contact structure. A passivation layer is formed overlying the metal layer. Preferably, an air gap layer is coupled between the passivation layer and the metal layer, the air gap layer allowing a portion of the metal layer to be free standing. Depending upon the embodiment, a portion of the air gap layer may be filled with silicon bearing nanoparticles, which may be oxidized at low temperatures. This oxidized layer provides mechanical support and low k dielectric characteristics. Preferably, a portion of the air gap layer is filled with a low k dielectric material as well.

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