Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-01-28
2003-01-28
Thomas, Tom (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S371000, C438S199000
Reexamination Certificate
active
06512273
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to an integrated circuit manufacturing process and structure, and in particular a method and structure for improving hot carrier injection lifetimes for devices having very shallow junction depths.
BACKGROUND OF THE INVENTION
Hot carrier effects are an important source of device degradation in MOSFET's. They are caused by high electric fields which usually occur near curved regions of the device junctions, and they increase as gate oxide thickness decreases or as junction depth decreases. Hot carriers can cause several deleterious effects in the device. First, electrons which acquire greater than 1.5 eV of energy can lose the energy via impact ionization which generates electron-hole pairs. In the extreme, this electron-hole pair generation can lead to avalanche breakdown. Second, the hot carriers can overcome the potential energy barrier between the silicon of the substrate and the SiO
2
of the gate oxide, thereby causing hot carriers to become injected into the gate oxide. If electron-hole pairs are created, the electrons add to the drain current, whereas the holes contribute to the parasitic substrate current, I
sub
. Hot carriers which pass through the gate oxide into the gate electrode produce a gate current, whereas those which remain trapped in the gate oxide affect the device threshold voltage. Furthermore, the trapped charge accumulates with time.
Device design methods such as double-diffused drains and lightly-doped drains (LDD), also known as extension implants, have been employed to reduce hot-carrier degradation. In the LDD structure, the drain is formed by two implants. A first source/drain implant known as the LDD or extension implant having a relatively light dopant dose extends under the gate electrode. It may be formed by using the gate as an implant mask. A second implant known as the S/D implant having a relatively heavy dopant dose is generally implanted further removed from the gate, and may be formed using the gate with sidewall spacers thereon as an implant mask. The use of the LDD structure allows the maximum electric field in the channel region to be lowered by sharing the voltage drop between the channel and drain regions. This can reduce hot-carrier currents by orders of magnitude. Lowering the dopant dose in the LDD regions is critical as device dimensions, particularly gate length and junction depths, decrease. This is because the smaller dimensions, including smaller radius of curvature for junction and LDD edge regions, can still produce a very high electric field near the gate edge and result in hot carrier injection problems. Current processes can yield electric fields greater than 1.5×10
7
V cm
−1
, whereas in order to obtain acceptable hot carrier lifetime, fields should not exceed approximately 6×10
6
V cm
−1
.
The use of tilted channel implants (TCI) is another source of hot carrier generation, which has become important as gate dimensions have decreased. TCI was developed as a method of providing control over the amount of charge under the gate, and therefore reducing short channel effects and improving threshold voltage stability. A description of angled implants to stabilize threshold voltage without blanket channel implant (i.e., TCI) is given in U.S. Pat. No. 5,874,329 by Neary et al, which is hereby incorporated by reference. TCI, which has a characteristic double-elliptical shape extending into the channel region from the edges of the gate and overlapping beneath the center of the gate, replaces the conventional blanket channel implant, which was done prior to gate formation. A typical peak channel dopant concentration using TCI is 1.5−3×10
18
cm
−3
compared with 1×10
18
cm
−3
for blanket channel implants. This higher value is necessary for TCI due to its sharper drop of dopant concentration with depth as compared to a uniformly doped channel. The higher peak dopant concentration that occurs near the Si/SiO
2
interface contributes to the generation of hot carriers.
Disposable gate sidewall spacer technology has been developed in the prior art. One reason therefor was to enable the use of a high-temperature anneal for S/D and gate doped regions. Prior to the use of disposable spacers, the LDD regions were formed, then spacers were deposited and etched, followed by S/D and gate doping, wherein the S/D region was defined by the spacers. As a result, the LDD regions were subjected to the S/D anneal, which limited the maximum time and temperature of the S/D anneal. The ideal anneal profiles for LDD and S/D are: 1) a short, high-temperature anneal “spike” in a Rapid Thermal Anneal (RTA) machine for the LDD implant in order to ensure very shallow junctions of the extensions; and 2) a longer, higher-temperature anneal for the S/D implant. The high temperature S/D anneal acts: a) to drive dopants deeper in the source/drain region so as to reduce junction capacitance, and b) to drive dopants through the polysilicon gate to the polysilicon/dielectric interface so as to prevent poly depletion effects due to the altered workfunction. Use of disposable spacers allows both of the above ideal anneal profiles to be employed. A disposable spacer is formed to act as a S/D mask, then S/D is implanted, followed by the high-temperature S/D anneal. The disposable spacer is then removed and the LDD region is implanted, followed by the rapid spike LDD anneal.
Another use of disposable spacers is to allow a TCI to be performed subsequent to S/D implant and anneal. The S/D implant and anneal can be performed first while gate sidewall spacers are in place. The sidewall spacers are then removed, and TCI and LDD implants are performed. Any anneals following TCI and LDD implantation employ the lowest usable temperature for the shortest usable time. In this way, particularly for n-channel devices where the boron TCI has high diffusivity, the lateral diffusion of the TCI during S/D anneal can be avoided and lateral diffusion of the TCI during subsequent anneals can be minimized, thus providing improved control of channel implant profile and Vt. Accordingly, the channel dopant can be placed with great accuracy. The TCI dose can also be lowered compared with TCI performed before S/D implant and anneal. If TCI is implanted prior to S/D implant and anneal, there is a loss of channel implant concentration due to thermal out-diffusion and/or transient enhanced diffusion caused by damage during the heavy dose S/D implant. However, if TCI is implanted subsequent to S/D implant and anneal, such channel implant concentration loss is comparatively very small, so the TCI dose can be lowered. Consequently, the TCI concentration near the gate edge is lower, thus lowering the electric field which generates hot carriers.
In order to provide masking and alignment for the subsequent silicide formation when using disposable spacers (which was provided by the S/D masking spacers in single-spacer technology), a second set of gate sidewall spacers is then formed after LDD anneal. These second spacers remain in place and may provide other benefits in addition to their use as silicide masks, as will be described hereinafter.
When the second, permanent spacers are formed from a material which has a dielectric constant higher than that of the gate insulator, the drive current performance of the MOSFET's is improved by the high gate-fringing field, which allows the potential of the gate electrode to be applied to the region in the substrate under the sidewalls, thereby promoting inversion in that region. This is particularly important in MOSFET structures having offset gate structures where the S/D region is offset from, i.e., barely overlapping, the gate. This offset alleviates short channel effects, prevents punch-through, and significantly lowers the parasitic Miller capacitance. MOSFET structures have been proposed using silicon nitride spacers, as described by Kumagai et al in U.S. Pat. No. 5,302,845, and using non-doped polysilicon spacers as described by Shimizu et al
Cherian Sunny
Krivokapic Zoran
Milic Ognjen
Advanced Micro Devices , Inc.
Fisher Gerald
Owens Douglas W.
Thomas Tom
Wenocur Deborah
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