Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Patent
1997-07-10
1998-09-08
Le, Vu A.
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
36523006, 365149, 327534, 327538, 327540, H03K 301
Patent
active
058055096
ABSTRACT:
A method and structure for generating a boosted word line voltage for a memory array, such as a DRAM array. To ensure that an adequate voltage is applied to the word line of the memory array during write operations, the word line driver circuit is connected to a boost voltage generator which provides a substantially constant, regulated voltage which is boosted to a level which is approximately equal to the V.sub.cc supply voltage plus the threshold voltage of the memory cell pass transistor. A bias voltage generator provides a negative voltage which is used to bias the substrate of the memory array. The boosted voltage generator and the bias voltage generator can be operated in response to the same clock signal used to operate the memory array. A latch-up prevention circuit is provided to ensure that the word line driver circuit does not latch-up during power-on before an adequate boost voltage has been established.
REFERENCES:
patent: 4585954 (1986-04-01), Hashimoto
patent: 5267201 (1993-11-01), Foss et al.
patent: 5329168 (1994-07-01), Sugibayashi
patent: 5335205 (1994-08-01), Ogihara
patent: 5359552 (1994-10-01), Dhong et al.
patent: 5469387 (1995-11-01), Kim
patent: 5521871 (1996-05-01), Choi
patent: 5524095 (1996-06-01), Someya et al.
Horiguchi et al., "Dual-Operating-Voltage Scheme for a Single 5-V 16-Mbit DRAM", IEEE Journal of Solid-State Circuits, vol. 23, No. 5, Oct. 1988, pp. 1128-1132.
Fujii et al., "Session 16: Dynamic RAMs FAM 16.6: A 45ns 16Mb DRAM with Triple-Well Structure", ISSCC 89 / Friday, Feb. 17, 1989, pp. 248, 249 and 354.
Arimoto et al., "A 60ns 3.3V 16Mb DRAM", IEEE International Solid-State Circuits Conference, 1989, pp. 244 and 352.
Taylor et al., "A 1-Mbit CMOS Dynamic RAM with a Divided Bitline Matrix Architecture", IEEE Journal of Solid-State Circuits, vol. sc-20, No. 5, Oct. 1985, pp. 894-902.
Takeshima et al., "Session 16: Dynamic RAMs FAM 16.5: A 55ns 16Mb DRAM", ISSCC 89 / Friday, Feb. 17, 1989, pp. 246, 247 and 353.
Taniguchi et al., "Fully Boosted 64K Dynamic RAM with Automatic and Self-Refresh", IEEE Journal of Solid-State Circuits, vol. SC-16, No. 5, Oct. 1991, pp. 492-498.
Leung Wingyu
Lin Jeffrey J.
Klivans Norman R.
Le Vu A.
Monolithic System Technology, Inc.
LandOfFree
Method and structure for generating a boosted word line voltage does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and structure for generating a boosted word line voltage , we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and structure for generating a boosted word line voltage will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1289714