Method and structure for forming self-aligned, dual stress...

Details Method and structure for forming self-aligned, dual stress... Method and structure for forming self-aligned, dual stress...

2007-07-12

2009-08-04

Dickey, Thomas L (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S069000, C257S351000, C257SE21632

Reexamination Certificate

active

07569892

ABSTRACT:
A method for forming a self-aligned, dual stress liner for a CMOS device includes forming a first type stress layer over a first polarity type device and a second polarity type device, and forming a sacrificial layer over the first type nitride layer. Portions of the first type stress layer and the sacrificial layer over the second polarity type device are patterned and removed. A second type stress layer is formed over the second polarity type device, and over remaining portions of the sacrificial layer over the first polarity type device in a manner such that the second type stress layer is formed at a greater thickness over horizontal surfaces than over sidewall surfaces. Portions of the second type stress liner on sidewall surfaces are removed, and portions of the second type stress liner over the first polarity type device are removed.

REFERENCES:
patent: 4851370 (1989-07-01), Doklan et al.
patent: 5506169 (1996-04-01), Guldi
patent: 5538916 (1996-07-01), Kuroi et al.
patent: 5580815 (1996-12-01), Hsu et al.
patent: 5620919 (1997-04-01), Godinho et al.
patent: 5633202 (1997-05-01), Brigham et al.
patent: 5633552 (1997-05-01), Lee et al.
patent: 5668403 (1997-09-01), Kunikiyo
patent: 5707889 (1998-01-01), Hsu et al.
patent: 5847463 (1998-12-01), Trivedi et al.
patent: 5851893 (1998-12-01), Gardner et al.
patent: 5891798 (1999-04-01), Doyle et al.
patent: 5908312 (1999-06-01), Cheung et al.
patent: 5936300 (1999-08-01), Sasada et al.
patent: 5985737 (1999-11-01), Wu
patent: 6040619 (2000-03-01), Wang et al.
patent: 6046494 (2000-04-01), Brigham et al.
patent: 6146975 (2000-11-01), Kuehne et al.
patent: 6214733 (2001-04-01), Sickmiller
patent: 6228777 (2001-05-01), Arafa et al.
patent: 6261924 (2001-07-01), Mandelman et al.
patent: 6306742 (2001-10-01), Doyle et al.
patent: 6395610 (2002-05-01), Roy et al.
patent: 6436848 (2002-08-01), Ramkumar
patent: 6476462 (2002-11-01), Shimizu et al.
patent: 6509230 (2003-01-01), Roy et al.
patent: 6515351 (2003-02-01), Arafa et al.
patent: 6573172 (2003-06-01), En et al.
patent: 6653181 (2003-11-01), Hergenrother et al.
patent: 6724053 (2004-04-01), Divakaruni et al.
patent: 6825529 (2004-11-01), Chidambarrao et al.
patent: 7002209 (2006-02-01), Chen et al.
patent: 7205615 (2007-04-01), Tsutsui et al.
patent: 7288451 (2007-10-01), Zhu et al.
patent: 2006/0079046 (2006-04-01), Yang et al.
T. G. Ference et al.; “The Combined Effects of Deuterium Anneals and Deuterated Barrier-Nitride Processing on Hot-Electron Degradation in MOSFET's;” IEEE Transactions on Electron Devices, vol. 46, No. 4, Apr. 1999; pp. 747-753.
J.H. Stathis; “Reliability limits for the gate insulator in CMOS technology;” IBM J. Res. & Dev., vol. 46, No. 2/3, Mar./May 2002; pp. 265-286.
T.H. Ning; “Why BiCMOS and SOI BiCMOS?;” IBM J. Res. & Dev., vol. 46, No. 2/3, Mar./May 2002; pp. 181-186.

Affiliated with

Also associated with

Rating

Method and structure for forming self-aligned, dual stress... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method and structure for forming self-aligned, dual stress..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and structure for forming self-aligned, dual stress... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4091905