Method and structure for fabricating bonded substrate...

Semiconductor device manufacturing: process – Bonding of plural semiconductor substrates

Reexamination Certificate

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C438S406000, C438S419000, C257SE21090, C257SE23005

Reexamination Certificate

active

07598153

ABSTRACT:
A method for fabricating bonded substrate structures, e.g., silicon on silicon. In a specific embodiment, the method includes providing a thickness of single crystal silicon material transferred from a first silicon substrate coupled to a second silicon substrate. In a specific embodiment, the second silicon substrate has a second surface region that is joined to a first surface region from the thickness of single crystal silicon material to form of an interface region having a first characteristic including a silicon oxide material between the thickness of single crystal silicon material and the second silicon substrate. The method includes subjecting the interface region to a thermal process to cause a change to the interface region from the first characteristic to a second characteristic. In a specific embodiment, the second characteristic is free from the silicon oxide material and is an epitaxially formed silicon material provided between the thickness of single crystal silicon material and the second silicon substrate. The method includes maintaining the interface region free of multiple voids during the thermal process to form the epitaxially formed silicon material to electrically couple the thickness of single crystal silicon material to the second silicon substrate.

REFERENCES:
patent: 2981877 (1961-04-01), Noyce
patent: 4363828 (1982-12-01), Brodsky et al.
patent: 4585671 (1986-04-01), Kitagawa et al.
patent: 4696758 (1987-09-01), Ovshinsky et al.
patent: 5120394 (1992-06-01), Mukai
patent: 5670411 (1997-09-01), Yonehara et al.
patent: 5789030 (1998-08-01), Rolfson
patent: 5877070 (1999-03-01), Goesele et al.
patent: 6013563 (2000-01-01), Henley et al.
patent: 6033974 (2000-03-01), Henley et al.
patent: 6100166 (2000-08-01), Sakaguchi et al.
patent: 6103599 (2000-08-01), Henley et al.
patent: 6171965 (2001-01-01), Kang et al.
patent: 6180496 (2001-01-01), Farrens et al.
patent: 6287941 (2001-09-01), Kang et al.
patent: 6326279 (2001-12-01), Kakizaki et al.
patent: 6368930 (2002-04-01), Enquist
patent: 6455399 (2002-09-01), Malik et al.
patent: 6500694 (2002-12-01), Enquist
patent: 6534381 (2003-03-01), Cheung et al.
patent: 6563133 (2003-05-01), Tong
patent: 6586785 (2003-07-01), Flagan
patent: 6627531 (2003-09-01), Enquist
patent: 6653212 (2003-11-01), Yamanaka et al.
patent: 6699531 (2004-03-01), Fukiage
patent: 6716751 (2004-04-01), Todd
patent: 6723606 (2004-04-01), Flagan
patent: 6740909 (2004-05-01), Enquist
patent: 6756281 (2004-06-01), Enquist
patent: 6771410 (2004-08-01), Bourianoff
patent: 6804062 (2004-10-01), Atwater
patent: 6818529 (2004-11-01), Bachrach et al.
patent: 6821825 (2004-11-01), Todd et al.
patent: 6822326 (2004-11-01), Enquist et al.
patent: 6858107 (2005-02-01), Ghyselen et al.
patent: 6858517 (2005-02-01), Martinez et al.
patent: 6864585 (2005-03-01), Enquist
patent: 6867073 (2005-03-01), Enquist
patent: 6875671 (2005-04-01), Faris
patent: 6884696 (2005-04-01), Aga et al.
patent: 6900115 (2005-05-01), Todd
patent: 6902987 (2005-06-01), Tong et al.
patent: 6905557 (2005-06-01), Enquist
patent: 6962858 (2005-11-01), Neyret et al.
patent: 6962859 (2005-11-01), Todd et al.
patent: 7019339 (2006-03-01), Atwater
patent: 7029995 (2006-04-01), Todd et al.
patent: 2002/0168868 (2002-11-01), Todd
patent: 2002/0173113 (2002-11-01), Todd
patent: 2002/0190269 (2002-12-01), Atwater
patent: 2002/0197831 (2002-12-01), Todd et al.
patent: 2003/0082300 (2003-05-01), Todd et al.
patent: 2003/0095340 (2003-05-01), Atwater
patent: 2003/0111013 (2003-06-01), Oosterlaken et al.
patent: 2003/0119280 (2003-06-01), Lee et al.
patent: 2003/0129545 (2003-07-01), Kik
patent: 2003/0203593 (2003-10-01), Beaman
patent: 2003/0230629 (2003-12-01), Bourianoff
patent: 2003/0230778 (2003-12-01), Park et al.
patent: 2004/0214434 (2004-10-01), Atwater
patent: 2005/0026400 (2005-02-01), Todd et al.
patent: 2005/0026432 (2005-02-01), Atwater
patent: 2005/0085049 (2005-04-01), Atwater
patent: 2005/0092235 (2005-05-01), Brabant et al.
patent: 2005/0142879 (2005-06-01), Atwater
patent: 2005/0153524 (2005-07-01), Maa et al.
patent: 2005/0208740 (2005-09-01), Todd
patent: 2005/0245049 (2005-11-01), Akatsu et al.
patent: 2005/0247924 (2005-11-01), Atwater
patent: 2005/0250302 (2005-11-01), Todd et al.
patent: 2005/0272222 (2005-12-01), Flamand et al.
patent: 2005/0275067 (2005-12-01), Atwater
patent: 2006/0019464 (2006-01-01), Maa et al.
patent: 2006/0021565 (2006-02-01), Zahler
patent: 2006/0024435 (2006-02-01), Holunga
patent: 2006/0030124 (2006-02-01), Maa et al.
patent: 2006/0030131 (2006-02-01), Richardson
patent: 2006/0060943 (2006-03-01), Mohamed et al.
patent: 2006/0071213 (2006-04-01), Ma et al.
patent: 2006/0088985 (2006-04-01), Haverkort et al.
patent: 2006/0108688 (2006-05-01), Richardson
patent: 2006/0112986 (2006-06-01), Atwater
patent: WO 99/08316 (1999-02-01), None
Ahn, et. al., Stability of Interfacial Oxide Layers during Silicon Wafer Bonding, Journey of Applied Physics, 65(2), Jan. 15, 1989, pp. 561-563.
Ahn, et. al., Growth, Shrinkage, and Stability of Interfacial Oxide Layers Between Directly Bonded Silicon Wafers, Applied Physics A 50 (1990), pp. 85-94.
Huang et. al., The Lower Boundary of the Hydrogen Concentration required for Enhancing Oxygen Diffusion and Thermal Donor Formation in Czochralski Silicon, Journal of Applied Physics 98, 033511 (2005).
Ling et. al., Relationship Between Interfacial Native Oxide Thickness and Bonding Temperature in Directly Bonded Silicon Wafer Pairs, Journal of Applied Physics 71 (3), Feb. 1, 1992, pp. 1237-1241.
Yamazaki et. al., Influence of Annealing Ambient on Oxygen Out-Diffusion in Czochralski Silicon, Journal of Applied Physics, vol. 87, No. 9, May 1, 2000, pp. 4194-4197.
Agarwal, et. al., Efficient Production of Silicon-on-Insulator Films by Co-Implantation of the He+ with H+, Applied Physics, Mar. 2, 1998, Letters, vol. 72, No. 9.
Bennett et al., Complete Surface Exfoliation of 4H-SiC by H+- and Si+ Coimplantation, Applied Physics Letters, vol. 76, No. 22, May 29, 2000.
Brendel, A Novel Process for Ultrathin Monocrystalline Silicon Solar Cells on Glass, 14thEuropean Photovoltaic Solar Energy Conference, Jun. 30 to Jul. 4, 1997, Barcelona, Spain.
Brendel, Crystalline Thin-film Silicon Solar Cells from Layer-Transfer Processes: A Review, Proc. 10thWorkshop on Crystalline Silicon Solar Cell Materials and Processes, Aug. 13-16, 2000, Copper Mountain, USA, ed. by B.L. Sopori, (NREL, Golden, 2000).
Deboer, Low Temperature Epitaxial Silicon Growth Using Electron Cyclotron Resonance Plasma Deposition, Dissertation, Iowa State University, Ames, IA 1995.
Deboer et al., Preparation and Properties of High Quality Crystalline Silicon Films Grown by ECR Plasma Deposition, IEEE, Hawaii, Dec. 5-9, 1994.
De Moor, Technology Development for 3D Integration at IMEC “3D Architectures for Semiconductor Integration and Packaging”, Tempe AZ Jun. 13-15, 2005.
Deng et. al., High Efficiency and High Rate Deposited Amorphous Silicon-Based Solar Cells, Phase II, Annual Technical Progress Report, Sep. 1, 2002 to Aug. 31, 2003 NREL Subcontract No. NDY-2-30630-08.
Du et. al., Impact of Hydrogen dilution on Microstructure and Optoelectronic Properties of Silicon Films Deposited using Trisilane, J. Phys D: Appl. Phys. 38 (2005) pp. 838-842.
Duo et al., Comparison Between the Different Implantation Orders in H+ and He+ Coimplantation, Journal of Physics D: Applied Physics, 34, 477-482, 2001.
Ellis Jr., et. al., Chemical Vapor Deposition of Boron-Doped Hydrogenated Amorphous Silicon, App. Phys. Lett, 47 (2), Jul. 15, 1985, p. 135.
Feijoo et al., Prestressing of Bonded Wafers. Proceedings of the First International Symposium on Semiconductor Wafer Bonding: Science, Technology and Applications, The Electrochemical Society, vol. 92-7, New York, NY 1992.
Garrou, 3D Integration: A Status Report “3D Architectures for Semiconductor Integration and Packaging”, Tempe AZ Jun. 13-15, 2005.
Gösele, Semiconductor Wafer Bonding: Science Technology and Applications, Electrochemical Society Proceedings, vol. 97-36, pp. 229-248, 1998.
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