Electronic digital logic circuitry – Multifunctional or programmable
Reexamination Certificate
2000-06-29
2002-12-17
Le, Don Phu (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
C326S101000
Reexamination Certificate
active
06496032
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to placing circuit blocks and routing interconnect bus lines on an integrated circuit in such a way as to reduce the die area and cost of the integrated circuit.
In many integrated circuits, such as DRAMs (Dynamic Random Access Memories) and SDRAMs (Synchronous DRAMs), there are many large logic blocks, such as input/output ports and row and column decoders, which send and receive electrical signals from each other. These signals are sent along highly conductive interconnect lines such as aluminum or copper interconnect. Alternately, polysilicon can be used. When several of these wires are routed together, the resulting structure is known as a bus. These buses can broadly be broken down into two types, global and local. Global buses run a comparatively long distance around the integrated circuit, connecting two or more logic blocks electrically. Local buses run to neighboring or adjacent logic blocks.
Global buses have a more detrimental impact on an integrated circuit's die size and performance than do local buses. First of all, global buses are longer in length, and therefore, for a given width, take up more surface area on the integrated circuit. Second of all, logic is generally layed out in rows of gates, with routing channels for wires above and below the rows of gates. This is true whether the logic is layed out in the form of a gate array, hand crafted logic, or done by a program such as an auto place and router. Global buses generally use these routing channels, meaning the channels need to be wider.
Also, since global buses are longer in length than local buses, the amount of parasitic capacitance between each line in the bus to the substrate, active areas, power lines and the like, is increased. Furthermore, the fringing capacitance between lines in the bus increases with line length. In general, larger devices are required to drive this extra capacitance, resulting in a larger die size and higher power consumption. Also, the MTBF (Mean Time Between Failure) for an integrated circuit decreases with the increasing temperature that comes with increasing power dissipation. Therefore, long term reliability is also reduced by an increase in the amount of global buses on an integrated circuit.
Table
1
is a command decoder functional truth table of a Synchronous DRAM integrated circuit. Signal levels at inputs {overscore (CS)} (Chip Select), {overscore (RAS)} (Row Address Strobe), {overscore (CAS)} (Column Address Strobe), {overscore (WE)} (Write Enable), and DSF (Define Special Function), are decoded on the integrated circuit into command signals such as LMR (Load Mode Register), LSMR (Load Special Mode Register), and the other entries in column
100
.
FIG. 1
shows a conventional command decoder logic block
110
for performing such decoding. Input signals on signal lines {overscore (CS)}
120
, {overscore (RAS)}
121
, {overscore (CAS)}
122
, {overscore (WE)}
123
, and DSF
124
are typically carried on signal lines coupled to input pads on the integrated circuit. These input signals are decoded into command signals and output on output command signal lines LMR
130
, LSMR
131
, RBA
132
, RBAWPB
133
, CBA
134
, CBA_AP
135
, BW(_AP)
136
, BST
137
, PCH
139
, PCH_ALL
139
, and AREF
140
. The input signal lines can be collectively referred to as input signal bus
150
. The output command signal lines can collectively be referred to as output command signal bus
160
.
Table
2
shows the assignment for each of the bank address bits BA<
1
:
0
>, and address bits A<
8
:
0
> in different command modes. For example, in the Load Mode Register state, the bits on A
0
to A
3
define the Burst Length for the device. Upon activating the Load Mode Register Command, specific address information is loaded into the command register, thus defining the SDRAM operation with respect to data bursting.
FIG. 2
shows a conventional block and routing placement for an SDRAM integrated circuit
200
. Integrated circuit
200
contains a plurality of input pads
210
-
220
, which are coupled to the group of logic blocks
230
by interconnecting wires
240
-
250
. Each pad
210
-
220
corresponds to one of the address inputs A<
8
:
0
> or BA<
1
:
0
>. The group of logic blocks
230
is coupled to destination blocks including the I/O (input/output) ports
255
, the X-decoder
260
, Y-decoders
270
and
271
, and mode registers
275
and
276
, by global buses
280
-
285
. Command decoder logic block (CDLB)
110
has input signal bus
150
as its inputs, and generates output command signal bus
160
as its output as described in FIG.
1
. Output command signal bus
160
couples to the group of logic blocks
230
. Some of the lines in output command signal bus
160
may also couple to the destination blocks; these lines are not shown for simplicity. This block and routing placement may be done by hand editing, autorouting, cell generation tools and the like. This type of placement has several global buses and lines routed around the area between the pads and the y-decoders. For example, global buses
280
,
281
,
282
,
283
,
284
, and
285
respectively couple the group of logic blocks
230
with the I/O ports
255
, the y-decoder
271
, the mode register
276
, the x decoder
260
, the mode register
275
, and the y-decoder
270
. The global buses
280
-
285
along with interconnect line
240
-
250
consume die area. For example, the group of logic blocks
230
can only be so close to the pads
210
-
220
as to allow for room for wires
240
-
250
to be run. Also, the y-decoders
270
and
271
and group of logic blocks
230
must be far enough apart to allow room for global buses
280
-
285
.
As the above makes clear, there is a great motive to reduce the amount and the length of busing on an integrated circuit.
SUMMARY OF THE INVENTION
In accordance with an embodiment of the present invention, an integrated circuit includes an input bus configured to receive a plurality of input signals. The input bus extends across a predetermined length of one side of the integrated circuit. The integrated circuit further includes a plurality of logic block circuits coupled to the input bus for receiving one or more of the input signals. Each of the logic block circuits are coupled to at least one of a plurality of destination blocks via a first set of interconnect buses. The logic block circuits are placed along the one side of the die such that the first set of interconnect buses extend substantially orthogonal to the input bus.
In another embodiment, the integrated circuit further includes a plurality of input buffers coupled to the input bus for providing the input signals on the input bus. A second set of interconnect buses couple the input buffers to the input bus, and a third set of interconnect buses couple the input bus to the logic block circuits. The second and third sets of interconnect buses extend substantially orthogonal to the input bus.
In another embodiment, the input buffers include a latch circuit for latching the input signals. The input buffers provide the latched input signals on the input bus synchronously with a clock signal.
In another embodiment, the input bus extends across a substantial portion of the length of one side of the integrated circuit.
In accordance with another embodiment of the present invention, a method for placing and routing circuit blocks in an integrated circuit includes the following steps: placing a plurality of destination circuit blocks in predesignated areas of the integrated circuit; extending an input bus across one side of the integrated circuit; placing a plurality of logic block circuits coupled to the input bus along the one side of the integrated circuit such that a first set of interconnect buses coupling the logic circuit blocks to the destination circuit blocks extend substantially orthogonal to the input bus.
In another embodiment, the method further includes the step of placing a plurality of input buffers along the one side of the integrated cir
C-Link Technology
Le Don Phu
Townsend and Townsend / and Crew LLP
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