Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1984-11-27
1987-03-31
Fears, Terrell W.
Static information storage and retrieval
Read/write circuit
Bad bit
365210, 371 21, G11C 1300
Patent
active
046548300
ABSTRACT:
Means are provided for replacing a defective row (or column) of memory in a fuse-array PROM which comprises disabling the defective row and programming a redundant row to respond to the address of the defective row. Means are also provided for reducing the swing between high and low address voltages.
The redundant row is connected via an AND gate through fuses to all ADDRESS and ADDRESS lines of the address buffer, so that the redundant row is always off until programmed. If a defective row is found, all memory cells in the defective row are disabled and the redundant row is programmed by selectively blowing fuses leading to the ADDRESS and ADDRESS lines thus causing the redundant row to respond to the address of the defective row.
REFERENCES:
patent: 4281398 (1981-07-01), McKenny et al.
patent: 4291394 (1981-09-01), Nakano et al.
patent: 4514830 (1985-04-01), Hagiwarn et al.
patent: 4538245 (1985-08-01), Smarandoiu et al.
Chan Albert
Chua H. T.
Gouldsberry Gary
Tsui Cyrus
Caserza Steven F.
Fears Terrell W.
Franklin Richard
MacPherson Alan H.
Monolithic Memories Inc.
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