Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2005-05-11
2008-11-25
Kim, Matt (Department: 2186)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
Reexamination Certificate
active
07457923
ABSTRACT:
A dynamic prediction is made whether a load instruction will miss a cache. Data is prefetched for the load instruction when a cache miss is predicted. Thus, the prefetch is only performed if a trigger event correlated with a cache miss for that load instruction is detected. This selective execution of the prefetches for a particular load instruction improves processor utilization and performance.
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Chou Yuan C.
Hsu Wei Chung
Fishburn John P
Gunnison Forrest
Gunnison McKay & Hodgson, L.L.P.
Kim Matt
Sun Microsystems Inc.
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