Method and structure for contacting two adjacent GMR memory bit

Details Method and structure for contacting two adjacent GMR memory bit Method and structure for contacting two adjacent GMR memory bit

2006-09-19

2008-07-08

Pham, Thanh V (Department: 2823)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S599000, C438S618000, C438S652000, C438S672000, C438S675000, C257SE21209, C257SE21658, C257SE21665, C257SE27006, C257SE27104

Reexamination Certificate

active

07396750

ABSTRACT:
A method and a structure are provided for improving the contact of two adjacent GMR memory bits. Two adjacent bit ends are connected by utilizing a single via.

REFERENCES:
patent: 6236079 (2001-05-01), Nitayama et al.
patent: 6376370 (2002-04-01), Farrar
patent: 2002/0173139 (2002-11-01), Kweon
patent: 2002/0195641 (2002-12-01), Fukuda et al.
patent: 2005/0099844 (2005-05-01), Witcraft et al.

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