Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2002-03-19
2004-05-25
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C700S109000, C700S120000, C700S121000, C702S083000, C702S084000, C702S134000, C702S172000, C356S328000, C356S334000, C356S336000, C356S337000, C382S144000, C382S145000
Reexamination Certificate
active
06742168
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to semiconductor fabrication technology, and, more particularly, to a method and a structure for calibrating a scatterometry-based metrology tool used to measure dimensions of features on a semiconductor device.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the operating speed of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for computers and electronic devices that operate at increasingly greater speeds. This demand for increased speed has resulted in a continual reduction in the size of semiconductor devices, e.g., transistors. That is, many components of a typical field effect transistor (FET), e.g., channel length, junction depths, gate insulation thickness, and the like, are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the transistor will operate. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical transistor to increase the overall speed of the transistor, as well as integrated circuit devices incorporating such transistors.
By way of background, an illustrative field effect transistor
10
, as shown in
FIG. 1
, may be formed above a surface
11
A of a semiconducting substrate or wafer
11
comprised of doped-silicon. In the process of forming integrated circuit devices, millions of transistors, such as the illustrative transistor
10
depicted in
FIG. 1
, are formed above a semiconducting substrate. The substrate
11
may be doped with either N-type or P-type dopant materials, for example. The transistor
10
may have a doped polycrystalline silicon (polysilicon) gate electrode
14
formed above a gate insulation layer
16
. The gate electrode
14
and the gate insulation layer
16
may be separated from doped source/drain regions
22
of the transistor
10
by a dielectric sidewall spacer
20
. The source/drain regions
22
for the transistor
10
may be formed by performing one or more ion implantation processes to introduce dopant atoms, e.g., arsenic or phosphorous for NMOS devices, boron for PMOS devices, into the substrate
11
. Shallow trench isolation regions
18
may be provided to isolate the transistor
10
electrically from neighboring semiconductor devices, such as other transistors (not shown). Additionally, although not depicted in
FIG. 1
, a typical integrated circuit device is comprised of a plurality of conductive interconnections, such as conductive lines and conductive contacts or vias, positioned in multiple layers of insulating material formed above the substrate. These conductive interconnections allow electrical signals to propagate between the transistors formed above the substrate.
During the course of fabricating such integrated circuit devices, a variety of features, e.g., gate electrodes, conductive lines, openings in layers of insulating material, etc., are formed to very precisely controlled dimensions. Such dimensions are sometimes referred to as the critical dimension (CD) of the feature. It is very important in modern semiconductor processing that features be formed as accurately as possible due to the reduced size of those features in such modem devices. The gate electrode
14
has a critical dimension
12
, i.e., the width of the gate electrode
14
, that approximately corresponds to the channel length
13
of the device when the transistor
10
is operational. Gate electrodes
14
may now be patterned to a width
12
that is approximately 180 nm, and further reductions are planned in the future, e.g., 120 nm. Since the width
12
of the gate electrode
14
corresponds approximately to the channel length
13
of the transistor
10
when it is operational, even slight variations in the critical dimension
12
of the gate electrode
14
as fabricated may adversely affect device performance. Moreover, at a given level of a wafer, features, e.g., gate electrodes, may be formed to a variety of different critical dimensions. Additionally, gate electrodes and/or shallow trench isolation structures at a given level may have differing critical dimensions.
Given the importance of forming features to very precise dimensions, semiconductor manufacturers typically measure the critical dimension of the resulting features to insure that manufacturing operations are producing features with dimensions that are within a previously determined acceptable range. Scatterometry-based metrology tools may be employed in determining the various dimensions. However, in situations where features having a variety of different critical dimensions must be measured, it is important that the metrology data obtained while measuring these structures be accurate, and that the scatterometry tool can be accurately calibrated as part of the overall metrology process.
The present invention is directed to a method and device that may solve, or at least reduce, some or all of the aforementioned problems.
SUMMARY OF THE INVENTION
The present invention is generally directed to a method and a structure for calibrating a scatterometry-based metrology tool used to measure dimensions of features on semiconductor devices. In one illustrative embodiment, the method comprises measuring a critical dimension of at least one production feature formed above a wafer using a scatterometry tool, measuring at least one of a plurality of grating structures formed above the wafer using the scatterometry tool, each of the grating structures having a different critical dimension, and correcting the measured critical dimension of the at least one production feature based upon the measurement of the at least one grating structure.
In another illustrative embodiment, the method comprises forming a plurality of production features above a wafer, forming a plurality of grating structures above the wafer, each of the grating structures comprised of a plurality of features each having a target critical dimension that thereby defines a critical dimension of the grating structure, each of the grating structures having a different critical dimension, measuring a critical dimension of at least one of the production features using a scatterometry tool, measuring at least one of the grating structures using the scatterometry tool to determine a measured critical dimension of at least one feature of the at least one grating structure, and correcting the measured critical dimension of the at least one production feature based upon a comparison between the measured critical dimension of the at least one feature on the at least one grating structure and the target critical dimension of the feature on the at least one grating structure.
REFERENCES:
patent: 5867276 (1999-02-01), McNeil et al.
patent: 5877680 (1999-03-01), Border
patent: 5880838 (1999-03-01), Marx et al.
patent: 6051348 (2000-04-01), Marinaro et al.
patent: 6081334 (2000-06-01), Grimbergen et al.
patent: 6245584 (2001-06-01), Marinaro et al.
patent: 6272392 (2001-08-01), Capodieci
patent: 6433878 (2002-08-01), Niu et al.
patent: 6448097 (2002-09-01), Singh et al.
patent: 6545753 (2003-04-01), Subramanian et al.
patent: 6561706 (2003-05-01), Singh et al.
patent: 6563578 (2003-05-01), Halliyal et al.
patent: 6583871 (2003-06-01), Rangarajan et al.
patent: 6643008 (2003-11-01), Stirton et al.
patent: 6657736 (2003-12-01), Finarov et al.
patent: 2002/0012854 (2002-01-01), Peng
patent: 2002/0107650 (2002-08-01), Wack et al.
patent: 2002/0131040 (2002-09-01), Niu et al.
patent: 2002/0135781 (2002-09-01), Singh et al.
patent: 2002/0176074 (2002-11-01), Hasan
patent: 0 727 715 (1996-08-01), None
patent: WO 02/13232 (2002-02-01), None
McGahan et al., “Design and performance of a normal-incidence optical critical dimension metrology system”, International Microprocesses and Nanotechnology Conference, Oct. 31, 2001, p. 238.
Advanced Micro Devices , Inc.
Kik Phallaka
Smith Matthew
Williams Morgan & Amerson P.C.
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