Method and structure for bonding layers in a semiconductor...

Details Method and structure for bonding layers in a semiconductor... Method and structure for bonding layers in a semiconductor...

1999-04-26

2002-05-14

Whitehead. Jr., Carl (Department: 2822)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S096000

Reexamination Certificate

active

06387736

ABSTRACT:

TECHNICAL FIELD
The invention relates in general to semiconductor devices, and more particularly to improving adhesion between certain layers that make up semiconductor devices.
BACKGROUND OF THE INVENTION
In the fabrication of semiconductor devices, layers, of dissimilar materials are sequentially formed on top of each other to define a multi-layer structure. In some instances, two electrically conducting layers that are formed in direct contact with each other exhibit poor adhesion. Poor adhesion between layers can have negative consequences, such as bubbling, blistering, and/or peeling at the interface between the two layers. Bubbling, blistering, or peeling degrades the electrical contact between the layers and in turn causes low yield and low reliability in fabricated semiconductor devices. The susceptibility of a device to the negative effects of poor adhesion between layers increases as the area of contact between poorly adhering layers increases.
A specific example of two layers that can exhibit poor adhesion to each other is titanium nitride and amorphous silicon.
FIG. 1
is a depiction of a layer stack
10
that includes, from the bottom layer to the top layer, an oxide layer
12
, a titanium nitride layer
14
, an n-doped amorphous silicon layer
16
, an intrinsic amorphous silicon layer
18
, and a p-doped silicon layer
20
. In the exemplary layer stack, the poor adhesion between the titanium nitride
14
and the n-doped amorphous silicon
16
tends to cause delamination problems when the linear distance of contact between the two layers exceeds approximately 200 &mgr;m in all directions.
One approach to improving adhesion between a titanium layer and a silicon layer in a semiconductor device is disclosed in U.S. Pat. No. 5,783,487 entitled “Method of Coupling Titanium to a Semiconductor Substrate and Semiconductor Device Thereof,” issued to Weeks et al. (hereinafter Weeks). The Weeks approach to improving adhesion between a titanium layer and a silicon layer involves forming an oxide layer between the titanium and silicon layers. The oxide layer exhibits good adhesion with both the titanium and the silicon layers. The Weeks approach is also utilized to improve adhesion between metal layers on the back side of a silicon chip. While the approach may work well for its intended purpose, the oxide layer deposited between the titanium and the silicon layers prevents direct contact between the titanium and the silicon layers. Depositing an oxide layer between the amorphous silicon
16
and titanium nitride
14
layers in the layer stack
10
of
FIG. 1
negatively affects the electrical characteristics of the layer stack by blocking electrical contact between the amorphous silicon and titanium nitride layers.
In view of the adhesion problems that exist between some layers in semiconductor devices, what is needed is a technique that improves bonding between poorly adhering layers, while maintaining some degree of electrical contact between the layers.
SUMMARY OF THE INVENTION
A method and structure for providing structural stability at an interface between two poorly adhering layers in a semiconductor device involve providing anchoring channels in one of the layers through which the other layer can be anchored to a third layer. Specifically, the structure and method are applicable to a three-layer stack having top and middle layers that tend to exhibit delamination when in direct contact with each other over large areas, and a bottom layer that bonds well to both the middle and top layers. In order to reduce susceptibility to delamination between the top and middle layers while, maintaining direct contact between the top layer and the middle layer, anchoring channels are created in the middle layer to allow the top layer to attach to the bottom layer, in effect tying the top layer down to the bottom layer.
The structure and method are particularly applicable to layer stacks in semiconductor devices, such as active pixel sensors, that include an oxide layer as the bottom layer, a titanium nitride layer as the middle layer, and an amorphous silicon layer as the top layer. In a preferred embodiment, the titanium nitride layer is deposited onto the oxide layer, and anchoring channels are created in the titanium nitride layer in order to expose portions of the oxide layer. The amorphous silicon layer is then deposited over the titanium nitride layer and into the anchoring channels in the titanium nitride layer. The anchoring channels provide direct contact between the amorphous silicon layer and the oxide layer. Although direct contact is provided between the amorphous silicon layer and the oxide layer, the contact between the two layers is not electrically conductive. That is, the anchoring channels are not similar to electrically conducting vias which provide conductive paths between layers. In order to prevent delamination between the titanium nitride layer and the amorphous silicon layer, the anchoring channels are preferably separated by 200 &mgr;m or less.
In another embodiment, the layer of titanium nitride is deposited onto the oxide layer, and portions of the titanium nitride layer are removed such that a pattern of isolated squares, or islands, of titanium nitride is created. Thus, in contrast to the first embodiment in which the patterned titanium nitride is continuous, in this second embodiment, the patterning of the titanium nitride forms isolated islands of the material. Amorphous silicon is then deposited over the titanium nitride islands and onto the exposed oxide layer, thereby anchoring the amorphous silicon layer to the oxide layer. In order to prevent delamination between the titanium nitride layer and the amorphous silicon layer, each of the titanium nitride islands preferably has at least one linear dimension that is less than 500 &mgr;m, preferably less than 200 &mgr;m.
An advantage of the invention is that yield and reliability of semiconductor devices formed with layers of marginal adhesion are improved because delamination is minimized. Moreover, structural stability is enhanced without a loss of electrical connectivity between the layers of the marginal adhesion. In addition, the improved adhesion can be achieved with little extra manufacturing cost.


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Annex to the European Search Report on European Patent Application No. EP 0 030 3451.

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