Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – Insulative material deposited upon semiconductive substrate
Reexamination Certificate
2000-08-18
2001-10-16
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
Insulative material deposited upon semiconductive substrate
C438S780000, C438S781000, C438S787000
Reexamination Certificate
active
06303525
ABSTRACT:
FIELD OF INVENTION
The present invention is generally directed to the manufacture of a semiconductor device. In particular, the present invention relates to a process that provides for improving the adhesion of methyl silsesquioxane (MSQ) film to a liner oxide.
BACKGROUND OF INVENTION
As devices scale down to the sub-micron level, electrical characteristics such as capacitance that were negligible in devices having dimensions in multiples of microns, have become significant. For example, in a sub-0.20 &mgr;m process there has been a renewed interest in materials with a low dielectric constant (i.e., “low k”).
A goal in processing sub-micron devices is to maintain a level of gate capacitance while minimizing the gate-to-source and gate-to-drain capacitance. As the oxide is made thinner the capacitance increases as shown in the relationship:
C
ox
=
ε
o
ε
SiO
2
t
ox
·
A
,
where
A=area of gate
&egr;
SiO
2
=dielectric constant (or relative permittivity of SiO
2
taken as 3.9)
t
ox
=oxide thickness
The gate-to-drain capacitance is especially critical for transistor performance as it is amplified during switching due to the Miller effect. For example, in a series of logic stages, the equivalent capacitive loading to the previous logic stage is the gate-to-source capacitance multiplied by a factor of 1 plus the gain of the transistor. If the transistor has a gain of 100, the observed input capacitance would be 101 times the gate-to-drain capacitance. Consequently, it is desirable to not alter the parameters that tend to increase that capacitance. Therefore, using a dielectric material having a lower dielectric constant lowers the capacitance. It is advantageous to use lower k materials throughout the integrated circuit design where possible to minimize the parasitic capacitance.
The requirement for low k materials for sub-quarter micron and smaller devices has renewed the interest in spin-on dielectrics such as methyl silsesquioxane (MSQ) and hydrogen silsesquioxane (HSQ). MSQ has a dielectric constant of ~2.9. The empirical formula of MSQ is CH
3
SiO
1.5
. The addition of organic side groups to the basic O—Si—O backbone results in improved crack resistance of the films. The structure has a lower density and hence a lower dielectric constant than that of SiO
2
.
In an example process, it is a challenge to integrate MSQ as a low k dielectric. MSQ and PECVD (plasma enhanced chemical vapor deposition) oxide do not adhere well to one another owing to the presence of methyl groups on the surface. The material has significant methyl content up to about 25%. The presence of methyl groups makes the film hydrophobic, as it is difficult to form SiOH bonds by breaking the Si—CH
3
bonds.
FIG. 1
depicts a substrate
100
having metal lines
110
. The de-lamination of MSQ
130
from the liner oxide
120
may degrade performance of the device
There exists a need to provide for the adhesion of MSQ to the PECVD oxide that resists de-lamination enabling the use of this low k dielectric to improve device yield and product performance.
SUMMARY OF INVENTION
The present invention is exemplified in a number of implementations, one of which is summarized below. It is a challenge to obtain sufficient adhesion of methyl silsesquioxane (MSQ) to aluminum alloys when MSQ is used as a gap-filling dielectric. Adhesion may be improved by using a liner dielectric that exhibits good adhesion to the aluminum on one hand, yet good adhesion to MSQ on the other. However, the MSQ layer may de-laminate if there is an abrupt interface between liner dielectric and the MSQ. A transition is made in the liner dielectric between silicon dioxide to a methyl-doped oxide, each film providing sufficient adhesion to aluminum alloy and MSQ, respectively.
A method for depositing a liner dielectric on a semiconductor substrate provides for sufficient adhesion of low dielectric constant spin-on materials. In an example embodiment, on a semiconductor substrate, there is a method of adhering a spin-on dielectric on a metal layer. A first-predetermined thickness of a liner dielectric is deposited on the metal layer. The liner dielectric has a chemical affinity to the metal layer. A transition layer of a second predetermined thickness is formed on the liner dielectric; the transition layer has less chemical affinity to the metal layer and increasing chemical affinity to the spin-on dielectric as the thickness of the transition layer increases. A third predetermined thickness of liner dielectric is deposited on the transition layer; the liner dielectric has a chemical affinity to the spin-on dielectric.
In another example embodiment, a method for adhering silsesquioxane compounds, provides a liner dielectric on an aluminum alloy metal layer on a semiconductor substrate, the method comprises placing the substrate in a CVD environment. A gas mixture comprising a precursor gas and N
2
O is introduced into the CVD environment. The ratio of precursor gas-to-N
2
O is predetermined. The gas mixture is reacted to deposit the liner dielectric of a predetermined thickness. An additional feature of this embodiment, is the during the reacting of the gas mixture, the precursor-to-N
2
O ratio may be adjusted so that silicon dioxide is deposited on the aluminum alloy metal layer a first predetermined thickness. By re-adjusting the precursor gas-to-N
2
O ratio, methyl doped oxide of a second predetermined thickness is deposited on the first predetermined thickness of the silicon dioxide. A further feature of this embodiment is wherein the re-adjusting of the precursor gas-to-N
2
O ratio produces a transition in the liner dielectric from a region of silicon dioxide to a region of methyl doped oxide.
REFERENCES:
patent: 5616202 (1997-04-01), Camilletti et al.
patent: 6153512 (2000-11-01), Chang et al.
patent: 6211062 (2001-04-01), Oda
patent: 6232237 (2001-05-01), Tamaoka et al.
patent: 487857-A2 (1992-06-01), None
patent: 751238-A2 (1997-01-01), None
patent: 881678-A2 (1998-12-01), None
Dang Trung
Philips Electronics No. America Corp.
Zawilski Peter
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