Electrical computers and digital processing systems: memory – Address formation – Address multiplexing or address bus manipulation
Reexamination Certificate
1999-04-21
2001-09-25
Yoo, Do Hyun (Department: 2185)
Electrical computers and digital processing systems: memory
Address formation
Address multiplexing or address bus manipulation
C711S170000, C711S173000, C714S006130, C714S702000, C365S230060, C365S230020
Reexamination Certificate
active
06295595
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates memory circuits. More specifically, the present invention relates to a method and structure to use a memory array having defective memory cells.
RELATED ART
FIG. 1
is block diagram of a conventional memory circuit
100
. Memory circuit
100
comprises a memory array
110
, an address decoder
120
, and a data tranceiver
130
. Typically, memory circuit
110
is accessed by an address bus ADDR coupled to address decoder
120
and a data bus DATA coupled to data tranceiver
130
. Some embodiments of data tranceiver
130
may be implemented using separate data receiving circuits and driving circuits. Address bus ADDR comprises N address lines, referred to as A[N−1], A[−2], . . . , A[
0
], where A[N−1] is the most significant bit of address bus ADDR. To avoid confusion, the individual bits of an address on address bus ADDR are also referred to by A[N−1], . . . , A[
0
], where A[N−1] is the most significant bit. A range of address lines (or address bits) A[s], A[s−1], . . . , A[t] is denoted as address lines (or address bits) A[s:t].
Typically, to read a data word from memory array
110
, the address of the desired data word is driven onto address bus ADDR. Address decoder
120
decodes the address to enable the appropriate word lines (not shown) of memory array
110
. Then memory array
110
drives the requested data word to data tranceiver
130
. Typically, memory array
110
drives very low voltage signals to data tranceiver
130
. Therefore, data tranceiver
130
converts the voltage levels of the data word received from memory array
110
to the voltage levels of data bus DATA and drives the requested data word onto data bus DATA. To write a data word into memory array
110
, an address is driven onto address bus ADDR and a data word is driven onto data bus DATA. Address decoder
120
decodes the address to enable the appropriate word lines of memory array
110
. Data tranceiver
130
converts the data word on data bus DATA to the voltage levels necessary to program memory array
110
.
To be competitive in the marketplace, memory circuits must have very high density, i.e., must have large memory arrays, and must be produced at very low cost. One major factor in the cost of producing a memory circuit is the defect rate of the memory circuit. The defect rate is typically expressed as the number of memory circuits that are defective out of a fixed number (typically 1000) of memory circuits produced. For example, if for every 1000 instances of memory circuit
100
, 50 instances are defective, memory circuit
110
has a defect rate of 50/1000. In general, large memory circuits have higher defect rates because large memory arrays are difficult to manufacture.
A single defective memory cell in memory array
110
renders memory circuit
100
defective. A common approach to lessen the severity of non-functional memory cells is to include redundant memory cells which can replace non-functional memory cells.
FIG. 2
is a block diagram of a conventional memory circuit
200
using redundant memory cells. Specifically, memory circuit
200
includes an address decoder
220
, a memory array
110
, a redundant memory array
210
, and a data tranceiver
230
. If memory array
110
does not contain any non-functional memory cells, memory circuit
200
behaves the same as memory circuit
100
with redundant memory array
210
being unused. However, if memory array
110
contains non-functional memory cells, address decoder
220
and data tranceiver
230
are configured to salvage memory circuit
200
by using memory cells from redundant memory array
210
in place of the non-functional memory cells of memory array
110
.
Typically, memory array
110
is divided into rows, columns, and/or blocks of memory cells. Similarly redundant memory array
210
is divided into rows, columns, and/or blocks of memory cells. For clarity, the term “partition” is used herein to refer to any group of memory cells including rows and columns of memory cells.
Typically, each partition in redundant memory array
210
is associated with a set of partitions in memory array
110
. If one of the partitions of memory array
110
contains non-functional memory cells (i.e., a non-functional partition), address decoder
220
and data tranceiver
230
are configured to use the associated partition in redundant memory array
210
in place of the non-functional partition of memory array
110
. Specifically, if address decoder
220
receives an address on address bus ADDR referencing the non-functional partition, address decoder enables the associated partition of redundant memory array
210
instead of the non-functional partition. On reads, data tranceiver
230
drives the data from the associated partition of redundant memory array
210
onto data bus DATA. On writes, data tranceiver
230
drives the data from data bus DATA to the associated partition in redundant memory array
210
. Thus, instances of memory circuit
200
which contain non-functional memory cells can be salvaged rather than discarded.
Typically, address decoder
220
and data tranceiver
230
contain non-volatile memory (not shown), such as FLASH memory cells, fuses, or anti-fuses, for storing redundancy configuration data. Before packaging, memory array
110
is tested for non-functional partitions, if a non-functional partition is discovered, address decoder
220
and data tranceiver
230
are configured to use the associated partition of redundant memory array
210
. Thus, by storing redundancy configuration data in non-volatile memory on memory circuit
200
, the use of redundant memory is transparent to end users.
If too many non-functional partitions of memory array
110
are associated with the same partition of redundant memory array
210
, memory circuit
200
can not replace all of the non-functional partitions. In this instance, memory circuit
200
is defective and must be discarded. To overcome this problem, many conventional methods to further reduce the defect rate of memory circuit
200
have been developed. For example, one method is to increase the size of redundant memory array
210
so that multiple partitions in redundant memory array
210
can be associated with each set of partitions in memory array
110
. A second method is to increase the number sets of partitions in memory array
110
and increasing the number of partitions in redundant memory array
210
while reducing the size of each set of partitions in memory array
110
, so that each partition of redundant memory array
210
is associated with a smaller number of partitions in memory array
110
. Most of these methods involve increasing the size of redundant memory array
210
to provide more redundancy for memory array
110
. However, one problem with increasing the size of redundant memory array
210
is the increased possibility that redundant memory array
210
may also contain non-functional memory cells. Thus, the decrease in defect rate produced by using these methods is partially offset by the possibility of non-functional partitions in redundant array
210
.
Another problem with using redundant memory arrays in memory circuits is the effect of a redundant memory array on the cost of the memory circuit. A major factor in the cost of a memory circuit is the semiconductor area required by the memory circuit. The larger the semiconductor area required for a memory circuit the greater the cost. Thus, redundancy schemes used to decrease the defect rate of memory circuits tend to increase the cost of each memory circuit because a relatively large semiconductor area is needed to accommodate redundant memory array
210
. Furthermore, to provide greater redundancy requires a larger redundant memory array, which requires even more semiconductor area. Thus, the additional cost of using redundant memory arrays significantly increases the cost of memory circuits. Hence, there is a ne
Goltman Gennady
Wildenberg Eli
Bever Hoffman & Harms LLP
Encarnacion Yamir
Mao Edward S.
Tower Semiconductor Ltd.
Yoo Do Hyun
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