Method and structure for a wafer level packaging

Details Method and structure for a wafer level packaging Method and structure for a wafer level packaging

2006-08-08

2006-08-08

Weiss, Howard (Department: 2814)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

Reexamination Certificate

active

07087464

ABSTRACT:
A method and structure for a wafer level package is provided, which utilizes a plurality of spacer walls on a semiconductor wafer or a transparent substrate, which has the ability to decide the position of the sealant. As a result, the dimension of a device is decided by the position of the sealant and the spacer walls, therefore, shrinking the distance between the photosensitive zone and the sealant will enhance the gross dies after performing a die sawing process to the whole semiconductor wafer. In addition, the semiconductor process decides the height of the spacer walls so that the yield will be improved due to the fact that a uniformity of the gap, which is between the semiconductor wafer and the transparent substrate, and the width of sealant, will be controlled.

REFERENCES:
patent: 5801068 (1998-09-01), Sooriakumar et al.
patent: 5923796 (1999-07-01), Feldman et al.
patent: 5936707 (1999-08-01), Nguyen et al.

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