Static information storage and retrieval – Read/write circuit – Bad bit
Patent
1987-10-05
1990-02-27
Moffitt, James W.
Static information storage and retrieval
Read/write circuit
Bad bit
365 75, G11C 700
Patent
active
049051962
ABSTRACT:
In order to reduce the down time of a computer (1, 4-8) caused by a fault or interrupt in the program run, program recovery points are provided which are time-dependent or can be preset in the main program of a useful program, and when these recovery points are reached, the computer status is stored in at least one fault-tolerant archival memory (5, 6). The computer status includes the status of the variables of a useful program being executed, the register status of the processor (1) and the register status of the input/output devices of the computer. During execution of the useful program, at least a part of the current computer status is stored in a main memory (4) and copied into an archival memory (6) when a program recovery point is reached. By using a small, fast cache memory (7) between the processor (1) and the main memory (4), the write cycles in the archival memories (5, 6) may be reduced since a variable is replaced in the main memory (4) only when it is displaced from the cache memory by a variable which may have been updated several times. A further improvement is achieved by using an associative stack (8) on the bus (2, 3) as the main (4) and the two archival memories (5, 6). All modifications in the main memory (4) are simultaneously entered into the stack (8) and into an archival memory (5) without involving the processor (1). In the stack (8), address data pairs are entered in the order of occurrence, a character recording the respective state of the stack and allocating locations to new address/data pairs. At the recovery point, only updated data need to be transferred into the archival memory. The main memory (4) can be integrated into an archival memory having a read/write memory area and a fault-tolerant tributary memory area. A cascaded memory or a virtual memory of the computer can also be used for saving the computer status.
REFERENCES:
patent: 3533082 (1970-10-01), Schnabel et al.
patent: 3736566 (1973-05-01), Anderson
patent: 3974480 (1976-08-01), Gernelle
patent: 4044337 (1977-08-01), Hicks et al.
patent: 4075693 (1978-02-01), Fox et al.
patent: 4164017 (1979-08-01), Randell et al.
patent: 4254477 (1981-03-01), Hsia et al.
patent: 4291388 (1981-09-01), Ecker, Jr. et al.
patent: 4300060 (1981-11-01), Yu
patent: 4419737 (1983-12-01), Yamaura et al.
patent: 4459658 (1984-07-01), Gabbe et al.
patent: 4513367 (1985-04-01), Chan et al.
Lee et al., "Rollback Propagation and Performance Evaluation of FTMR.sup.2 --A Fault-Tolerant Multiprocessor", Conference Proceedings, The 9th Annual Symposium on Computer Architecture, Apr. 26-29, 1982, Austin, Tex., IEEE Catalog No. 82, CH 1754-1, pp. 171-180.
Kubiak et al., "Penelope: A Recovery Mechanism for Transient Hardware Failures and Software Errors", FTCS 12th Annual Int'l Symposium-Fault-Tolerant Computing, 22-24 Jun. 1982, Santa Monica, Calif., IEEE Catalog 82CH1760-8, pp. 127-133.
Lee et al., "A Recovery Cache for the PDP-11", IEEE Transactions on Computers, Band C-29, Jun. 6, 1980, N.Y., pp. 546-549.
Feridun et al., "A Fault-Tolerant Multiprocessor System With Rollback Recovery Capabilities", Proc. 2nd Int'l Conf. on Distributed Computing System, Apr. 1981.
BBC Brown Boveri & Company Ltd.
Moffitt James W.
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