Method and stacked memory structure for implementing...

Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With heat sink means

Reexamination Certificate

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C257S707000, C257S713000, C257S719000

Reexamination Certificate

active

11138939

ABSTRACT:
A method and structure are provided for implementing enhanced cooling of a plurality of memory devices. The memory structure includes a stack of platters. A sub-plurality of memory devices is mounted on each platter. At least one connector is provided with each platter for connecting to the sub-plurality of memory devices. A heat sink is associated with the stack of platters for cooling the plurality of memory devices.

REFERENCES:
patent: 6861287 (2005-03-01), Farrar et al.
patent: 2002/0053726 (2002-05-01), Mikubo et al.
patent: 2005/0101056 (2005-05-01), Song et al.
patent: 2005/0133897 (2005-06-01), Baek et al.
patent: 2005/0141199 (2005-06-01), Chiou et al.

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