Method and resulting structure for fabricating test key...

Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure

Reexamination Certificate

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C257SE29024

Reexamination Certificate

active

07847288

ABSTRACT:
A method for fabricating test structures on a wafer for integrated circuits. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a plurality of integrated circuit chip structures on the semiconductor substrate and forming a plurality of MOS devices on a scribe line formed between a first group and a second group of integrated circuit chip structures concurrently using one or more similar processes during forming the plurality of integrated circuit chip structures. The method includes forming a first contact structure and a second contact structure. The first contact structure is coupled to a first MOS device in the plurality of MOS devices and the second contact structure is coupled to an Nth MOS device in the plurality of MOS devices, where N is an integer greater than 1.

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Requirement for Restriction/Election for U.S. Appl. No. 11/686,588, mailed on Dec. 17, 2007, 5 pages.

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