Method and resulting structure for fabricating test key...

Details Method and resulting structure for fabricating test key... Method and resulting structure for fabricating test key...

2007-03-15

2008-12-23

Chaudhari, Chandra (Department: 2891)

Semiconductor device manufacturing: process

With measuring or testing

Electrical characteristic sensed

C257SE21524

Reexamination Certificate

active

07468283

ABSTRACT:
A method for fabricating test structures on a wafer for integrated circuits. The method includes providing a semiconductor substrate, e.g., silicon wafer. The method includes forming a plurality of integrated circuit chip structures on the semiconductor substrate and forming a plurality of MOS devices on a scribe line formed between a first group and a second group of integrated circuit chip structures concurrently using one or more similar processes during forming the plurality of integrated circuit chip structures. The method includes forming a first contact structure and a second contact structure. The first contact structure is coupled to a first MOS device in the plurality of MOS devices and the second contact structure is coupled to an Nth MOS device in the plurality of MOS devices, where N is an integer greater than 1.

REFERENCES:
patent: 6881597 (2005-04-01), Asayama et al.

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