Method and resulting device for field inversion free multiple la

Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating

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257637, 257639, 257641, 257649, H01L 2358

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active

054612543

ABSTRACT:
There is described a multiple layer metallurgy, spin-on-glass multilayer metallurgy structure and method for making such structure for a one micrometer or less feature size integrated circuit with substantially free field inversion on a semiconductor substrate having a pattern of device regions therein. A passivation layer is located over the surfaces of the patterns. A pattern of openings are made through the passivation layer to at least some of the device regions which include source/drain regions. A patterned first metallurgy layer is in contact with the pattern of openings. A first via dielectric layer is located over the pattern of first metallurgy layer. A silicon-rich barrier dielectric layer is located over the first layer. A cured spin-on-glass layer is over the barrier layer. A silicon oxide second via dielectric layer is over the spin-on-glass layer. A pattern of openings is in the second via layer, spin-on-glass layer, barrier layer and first via layer. A patterned second metallurgy layer is in contact with the pattern of openings to make electrical contact with the first metallurgy layer wherein the multilevel metallurgy integrated circuit with substantially free field inversion is completed.

REFERENCES:
patent: 3760242 (1973-09-01), Duffy et al.
patent: 4901133 (1990-02-01), Curran et al.
patent: 4986878 (1991-01-01), Malazgirt et al.
patent: 5003062 (1991-03-01), Yen
patent: 5057897 (1991-10-01), Nanani et al.
patent: 5065222 (1991-11-01), Ishii
patent: 5082801 (1992-01-01), Nagata
"Field Inversion In CMOS Double Metal Circuits Due To Carbon Based SOGS" by D. Pramanik et al., Jun. 12-13, 1989, VMIC Conference.

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