Electrical computers and digital processing systems: support – Clock control of data processing system – component – or data...
Reexamination Certificate
2005-01-26
2008-10-28
Connolly, Mark (Department: 2115)
Electrical computers and digital processing systems: support
Clock control of data processing system, component, or data...
C713S401000, C713S500000, C711S100000
Reexamination Certificate
active
07444535
ABSTRACT:
A method and related apparatus for adjusting/calibrating timing of memory signals. In a preferred embodiment of the invention, reference signals of the same frequency and different phase are generated by a phase-lock loop. These reference signals are used to trigger sampling of signals for generating signals of different timing/delay; then timing/delay of memory signals, such as clock, command, data and data strobe, can be adjusted and calibrated. In this way, the invention can avoid the use of delay lines while adjusting/calibrating memory signals, so as to reduce the negative effects of characteristics shift and variation of delay lines.
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Hsieh Bowei
Liou Ming-Shi
Connolly Mark
Hsu Winston
VIA Technologies Inc.
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