Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2006-08-08
2006-08-08
Garbowski, Leigh M. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
07089510
ABSTRACT:
A method and program product for optimizing level converter placement in a multi supply integrated circuit. Each level converter is placed at a minimum power point to minimize net power and transitional delay from a first (low) voltage net source through the level converter and to a second (higher) voltage net sink. Then, inefficient level converters are eliminated. Level converters with fanin cones below a selected minimum cone size are deleted and low voltage sources to the deleted level converter reverted. Higher voltage level circuit elements receiving inputs from multiple level converters are replaced with equivalent low voltage circuit elements. Low voltage buffer driving level converters are both replaced by a single said level converter.
REFERENCES:
patent: 5517132 (1996-05-01), Ohara
patent: 5594368 (1997-01-01), Usami
patent: 5818256 (1998-10-01), Usami
patent: 5990706 (1999-11-01), Matsumoto et al.
patent: 6167554 (2000-12-01), Ishikawa et al.
patent: 6266798 (2001-07-01), Kanazawa et al.
patent: 6941534 (2005-09-01), Fukasawa
Chen et al., “On Gate Level Power Optimization Using Dual-Supply Voltages,” IEEE Trans. on VLSI Systems, vol. 9, No. 5, Oct. 2001, pp. 616-629.
Hamada et al., “A Top-Down Low Power Design Technique Using Clustered Voltage Scaling with Variable Supply-Voltage Scheme,” IEEE 1998 Custom ICs Conference, pp. 495-498.
Igarashi et al., “A Low-power Design Method Using Multiple Supply Voltages,” 1997 ACM, pp. 36-41.
Ishihara et al., “Lecel Conversion for Dual-Supply Systems,” ISLPED '-3, Aug. 25-27, 2003, pp. 164-167.
Kang et al., “Multiple-Vdd Scheduling/Allocation for Partitioned Floorplan,” Proc. of the 21stInt'l Conference on Computer Design, 2003, 7 pages.
Pangjun et al., “Clock Distribution Using Multiple Voltages,” ISLPED99, ACM 1999, pp. 145-150.
Usami et al., “Low-power Design Methodology and Applications utilizing Dual Supply Voltages,” 2000 IEEE, pp. 123-128.
Yeh et al., “Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-Based Designs,” 1999 ACM Design Automation Conference, 6 pages.
Lackey et al., Managing power and performance for System-on-Chip designs using Voltage Islands, Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design , Nov. 11, 2002, pp. 195-202.
Usami et al., Clustered Voltage Scaling Techniques for Low-Power Design, International Low Symposium on Low-Power Electronic Design, Apr. 1, 1995, pp. 3-8, Publisher: ACM Press.
Usami et al., Automated Low-Power Technique Exploiting Multiple Supply Voltages Applied To A Media Processor, IEEE Journal of Solid-State Circuits, Mar. 1, 1998, pp. 463-472, vol. 33, No. 3.
Yeh et al., Layout Techniques Supporting The Use of Dual Supply Voltages for Cell-Based Designs, Proc. ACM/IEEE Design Auto. Conf., Jun. 1, 1999, pp. 62-67.
Correale, Jr. Anthony
Kung David S.
Lamb Douglass T.
Pan Zhigang
Puri Ruchir
Garbowski Leigh M.
International Business Machines Corp.
Karra, Esq. Satheesh K.
Law Office of Charles W. Peterson, Jr.
Percello, Esq. Louis J.
LandOfFree
Method and program product of level converter optimization does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method and program product of level converter optimization, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method and program product of level converter optimization will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3650913